4.9152 MHz CPU CLOCK
The CLK output is a 33% duty cycle MOS clock driver designed to drive the iAPX 86, 88 processors directly. PCLK is a TTL level peripheral clock signal whose output frequency is 1/2 that of CLK, PCLK has a 50% duty cycle.
TEST POINTS
GIVES ACCESS TO a16-a19 both sides of the address pin latch (IC7)