Embedded Files
Sheet 1 - Power supply decoupling caps and spare gates
Sheet 1 - Power supply decoupling caps and spare gates
Clock Circuitry
Clock Circuitry
4.9152 MHz CPU CLOCK
14.7456 MHZ Crystal and D8284A INTEL CLOCK
14.7456 MHZ Crystal and D8284A INTEL CLOCK
Clock Outputs
Clock Outputs
The CLK output is a 33% duty cycle MOS clock driver designed to drive the iAPX 86, 88 processors directly. PCLK is a TTL level peripheral clock signal whose output frequency is 1/2 that of CLK, PCLK has a 50% duty cycle.
TEST POINTS
TETS POINT A
TETS POINT A
GIVES ACCESS TO a16-a19 both sides of the address pin latch (IC7)
TPA1-A19 LATCH OUTPUT
TPA1-A19 LATCH OUTPUT
TPA2-A19 FROM CPU DIRECT
TPA2-A19 FROM CPU DIRECT
TPA3-A18 CPU
TPA3-A18 CPU
TPA4-A18 LATCH OUTPUT
TPA4-A18 LATCH OUTPUT
TPA5-A17 LATCH OUTPUT
TPA5-A17 LATCH OUTPUT
TPA6-A19 CPU
TPA6-A19 CPU
TPA7-A16 CPU
TPA7-A16 CPU
TPA8-A16 LATCH OUTPUT
TPA8-A16 LATCH OUTPUT
8088 minimum mode is used in the Monarch - (MAX MODE USED ON PC XT)
8088 minimum mode is used in the Monarch - (MAX MODE USED ON PC XT)
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