During my Ph.D. period in Maryland, I worked in the field of Electronic design automation (EDA), with an emphasis on the design of high-performance, thermal-aware and highly reliable three dimensional integrated circuit (3D-IC).
3D-IC is an integrated circuit with a stack of planar chips. The chip stacking idea help 3D-IC achieve shorter communication distance, lower power consumption, and smaller area, making it a revolutionary technique to continue the scaling trajectory predicted by Moore's Law. My work covers several aspects of 3D-IC, such as:
1. Manufacturing. Through silicon via (TSV) is the vertical via connecting different layers, which is a crucial device in 3D-IC. Different from planer interconnects, TSV is a relatively large and its fabrication process is immature. We investigate the state-of-art manufacturing process for TSVs and study its influence on TSV's electrical, thermal, and reliability properties.
2. Low-power clock tree design. Excessive power density is a huge drawback of 3D-IC. We apply the clock gating technique to 3D clock tree to reduce its dynamic power consumption. We optimize the clock tree topology and select proper locations for clock gating, in order to achieve maximum power savings while accommodating different TSV usage limitations.
3. Electromigration-aware design. Electromigration (EM) is the one of TSV's primary failure causes. Different from planer interconnect, besides current, thermal variation and local thermal mechanical stress introduced during TSV's manufacturing process play huge roles in TSV's EM. We model TSV's EM based on its physics, develop general EM-aware methodologies and integrate our ideas into the prevailing 3D placement and clock tree synthesis tools.
4. Voltage noise in 3D power delivery network. In 3D CPUs, DRAMs and processor cores share the same power delivery network. Any power fluctuation in processor cores impacts the voltage noise in the DRAM, causing DRAM to lose its data over time. This project looks into the interaction between processor core activity and DRAM soft error rate, and we attempt to find the optimal trade off between 3D CPU performance and DRAM resiliency.