@ARTICLE{7010044,
author={T. Lu and A. Srivastava},
journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
title={Modeling and Layout Optimization for Tapered TSVs},
year={2015},
volume={23},
number={12},
pages={3129-3132},
keywords={circuit optimisation;current density;digital circuits;dynamic programming;integrated circuit layout;integrated circuit modelling;integrated circuit reliability;sputter etching;three-dimensional integrated circuits;3D IC;TSV electrical properties;TSV layout;TSV tapering effect;TSV-involved path delay;TSVs tapering;current crowding effect;current density distribution;current density model;cylindrical TSV;deep reactive ion etching-based manufacturing;digital circuit;dynamic programming-based heuristic;layout optimization;nonideal etching process;optimal wire configuration;second-order delay model;tapered TSV;through-silicon-via;Current density;Delays;Layout;Optimization;Passivation;Through-silicon vias;Wires;3-D IC;optimization;tapered through-silicon-via (TSV);tapered through-silicon-via (TSV).},
doi={10.1109/TVLSI.2014.2384042},
ISSN={1063-8210},
month={Dec},}