@INPROCEEDINGS{6702350,
author={T. Lu and A. Srivastava},
booktitle={3D Systems Integration Conference (3DIC), 2013 IEEE International},
title={Detailed electrical and reliability study of tapered TSVs},
year={2013},
pages={1-7},
keywords={electromigration;integrated circuit modelling;integrated circuit reliability;sputter etching;thermal stresses;three-dimensional integrated circuits;3D-IC;Elmore model;TSV;bonding materials;cell placement;clock network design;dry reactive ion etching;electromigration;gate placement;heat conductors;keep out zone;oxide layer;routing algorithms;tapering effect;thermal mechanical stress;wire routing;Current density;Delays;Reliability;Silicon;Stress;Thermal stresses;Through-silicon vias},
doi={10.1109/3DIC.2013.6702350},
month={Oct},}