Lesson 2: Logic gates

In this lab, you will use ISE to build schematic logic circuits by assembly of elementary logic gates. You will verify by simulation and by implementation on the board that the truth tables actually match your observations. It is through the interactive interface Isim, the simulation tool available with ISE, that you will program the simulation. Running on the board reuse the concepts introduced in the previous lesson …

You can find the file lecon2.pdf at the end sheet.

There are several ways to describe an electronic circuit. The main emerging two are:

• The schematic description: an electronic schematic. For this, Xilinx provides libraries for usual components (memory, counters ...) and of course the elementary gates.
• The textual description: description language VHDL (there are other languages, Verilog...).

Required Knowledge

Logic gates, Boolean algebra.

Objectives

In this lab, you will use ISE to build schematic logic circuits by assembly of elementary logic gates. You will verify by simulation and by implementation on the card that the truth tables actually match your observations. It is through the interactive interface Isim, the simulation tool available with ISE, that you will program the simulation. Running on the card reuse the concepts introduced in the previous lesson …

The project

You will design a component and its symbol combining two logic inputs in several ways. You will then instantiate this symbol in a diagram that integrates input / output ie switches and LEDs on the board. The simulation and synthesis will allow you to rebuild for all possible inputs truth tables for each output. Finally putting into practice two equivalent circuits will validate the achievements of this lesson.

Your first circuit

Once ISE launched, you can create a project TP2 with the same characteristics as the TP1 (Figure 2, Figure 3, Figure 4). Create a new project> new source selecting Schematic with as name firstsch.

Figure 24 Creation of firstsch

A firstsch.sch window opens in ISE. A schematic is necessarily composed of:

• Personal or predefined library symbols
• Connection wires between symbols and / or bus (array of wires)
• Input / output labels that indicate the inputs and outputs of the functions performed by the schematic

Save your files periodically...

You have already instantiated a symbol Ibuf8 and Obuf8 in the previous lesson. Nothing changed, to add a symbol in a diagram, use the button or the menu Add> Symbol. A list of symbol libraries will open on the left, by selection clicks followed by insertion clicks, you can place the components in your firstsch schematic. You will place successively the gates: AND2, INV, NAND2, NOR2, OR2, XNOR2, XOR2 (Figure 26). On each of the logic gate output, connect a wire and name them s0, s1, ... s6. ISE offers a quick way to automatically increment the name of your wires. Simply click on the new wire Increase the name with a first name initialized to s0, then every time you click on a wire, you name it and the name changes automatically s1, s2 ... It's pretty simple and very useful later .

Figure 25 increment wires names

Finally place two vertical wires a and b, from which you can draw wires to the inputs of the logic gates. Once the circuit is done, and to specify the ports of your component and then those of your symbol, place your I/O marker on the two inputs and 7 outputs. Again ISE offers a fast method, once the I/O Marker button selected, instead of clicking one by one on the wires, you can select a rectangular area on the diagram and all unconnected wires receive the I/O Marker with the default name of the marker. You should get the following circuit.

Figure 26 Schematic of firstsch

You already know the following steps to create a symbol. (Design Utilities> Create Schematic Symbol)

The simulation

Before continuing with the design, you can check step by step the good behavior of a component by simulation. It's a good working practice, each building block is tested before assembly.

Figure 27a Project Management Window

You need to select the simulation mode. You should get automatically the behevioral level simulation, if this is not the case it is up to you do it. Then it's always the same, select the component and run in the Processes window the action you want. Here, run the simulation by Isim Simulate Behavioral Model.

Isim will open the following window.

Figure 27b Starting Isim

Isim allows to observe the values ​​on each wire of the component at any time of the simulation. In particular Isim represents this evolution in a timing diagram where wires (or signals) are normally "0" or "1". For now your wires are either 'u' for undefined or 'x' for any. This is normal as a and b are not initialized!

You must therefore initiate a and b. In the timeline window under the Name column simply right click on a and select the Force constant drop down menu. It is then possible to initiate a to ‘0’. Do the same thing for b and force it to ‘0'.

Figure 27 Force a signal to 0 or 1

You can then continue the simulation to a new microsecond. Isim proposes four buttons that can

• replace the simulator at time zero,
• run the simulation,
• advance the simulation one time step, here 1.00us.
• run the simulator for a time step.

The wires become green, they are all set. Repeat the same operation by placing b to 1 then simulation for a time step. Then a to 1 and b to 0 and a simulation step, finally b to 1 for the last step of simulation. Using the zoom button you get an overview of the simulation for 5 microseconds.

Figure 28 Simulation of th 4 possibles cases

I'll let you check that the produced chronograms actually correspond to the used logic gates. The interactive use of Isim is suitable for components having a reduced number of combinations of inputs. You will learn later another way to use Isim in controlled mode, generating programmatically input values ​​at different times of the simulation.

Checking on the card

Before generating the binary code to be loaded on the board, you should as usual create the link to the FPGA pins. Remember the .ucf file, you are going here to create a new source TP2 of Implementation Constraints File to link a and b to switches to 0 and 1 and s0 to s6 outputs outputs to leds 0 to 6. You may choose your own links if you want. But however, here is the TP2.ucf file for the proposed configuration.

Figure 29 Creating the .ucf file

Nexys2 card

Nexys3 card

Do not forget to position your JTAG (Figure 13), you are ready to generate the code with Generate Programming File. Then with Adept load the firstsch.bit code to your Nexys board and again, validate your different gates trying different combinations for switches 0 and 1, the other switches have no effect.

Your turn now

I suggest you test your knowledge and your skills with a little exercise. You will now compare two circuits that, as you will see, do the same thing. I will guide you through the exercise.

1- Create a new project TP21 in ISE.

2- Create a new source of type schematic in this project the following circuit1.

3- In implementation mode, create the symbol associated to this circuit.

4- Create a second schematic new source circuit2.

5- We can create this second circuit. Selecting the complete circuit in circuit1. We make a copy/paste in circuit2. We remove the NAND2 and replace them by NOR2. Finally we change the name of s to t. We can use the Design Rules Check in Design Utilities to verify that the circuit is correct.

6- Create corresponding symbol for circuit2.

7- Create a third new type source schematic called toplevel.

8- By placing an instance of circuit1 and circuit2, make the connections on the same inputs a, b and c. Connect the two outputs s and t. Place your I/O Markers. Once saved, toplevel.sch must be the root of your project. The symbol before toplevel should be positioned. One can position it if needed via the left menu by a click on this symbol or in the Source menu by Set as Top Module.

9- Verify by simulation, on by launching Isim on toplevel, the outputs s and t are equivalent for all the combinations of a, b ​​and c.

10- Add a new TP21 source of type Implementation Constraints File. It is necessary in this file to associate a, b ​​and c to switches 0, 1 and 2, and outputs s and t to leds 0 and 1. We can copy the TP2.ucf file and edit it.

11- Remember the JTAG.

12- You can generate the binary code toplevel.bit and load it onto the board for verification. Both LEDs should turn on and off at the same time whatever are of the positions of switches 0, 1 and 2.

13- Still motivated! Find the two logical functions of these two circuits. Transform both logic functions to find a common one as simple as possible. Then instantiate a third circuit in toplevel to check that your transformations light the same way a third LED associated with a third output w.