Lesson 1: ISE for Nexys

In this lesson, you'll build your first simple design that will allow you to discover the inputs and outputs of the Nexys2 or Nexys3 boards. These I / O concepts will be used in all subsequent sessions. At the same time, this lab is to provide an introduction to the use of Xilinx and Digilent tools. Thanks to its simplicity, it is also a good example to understand the operation of the processing chain: how starting from a description code or a circuit diagram you can produce with ISE the binary mondesign.bit file. This file is then loaded onto the board on which the design specified with ISE is implemented...

The file lesson1.pdf is available at the end page!

We presume that the installations of ISE for implementation and compilation and Adept for the executions on the board were successfully completed.

Objectives

In this lesson, you'll be making your first simple design that will allow you to discover the inputs and outputs of the Nexys2 or Nexys3 cards. These I / O concepts will be used in all subsequent sessions. At the same time, this lab is to provide an introduction to the use of Xilinx and Digilent tools. Thanks to its simplicity, it is also a good example to understand the operation of the processing chain: how starting from a description code or a circuit diagram you produce, using ISE, mondesign.bit file. This file is then loaded onto the card on which the circuit specified in ISE is implemented.

The project

Let’s begin! Connect the board via the USB cable and put the power switch to the ON position. Launch the ISE 12.4 software! If you installed yourself ISE and the license you have already registered. For those who have access to a PC with a preinstalled tutorial class, you will only need to launch your application from the Windows Start menu in Xilinx ISE Design Suite 12.4> ISE Design Tools> Project Navigator.

Nexys2

Nexys3

For this first exercise, we will discuss the direct communication arrangements for the Nexys board, the 8 switches vector, 8 LEDs and four 7-segments displays. The first part is pretty simple: you will display on the 8 LED the values of the 8 switches: "0" or "1" for off or on. Then you will use the 4 switches SW0 to SW3 to represent a 4-bit binary coded number whose value can obviously be displayed in hexadecimal on a single display: x0 to xF or B000 to B1111 in binary or decimal 0-15 (Notation: b for binary number, x for hexadecimal number, nothing for decimal). You will set this value to be displayed on the rightmost of the four 7-segment displays. From this implementation I will propose other similar exercises that you can achieve alone.

In this first example, you'll mix the schematic design and design by code. The diagrams are specific to ISE, while the code respects the VHDL standard. This is a design language which you will discover progressively during the sessions. This does not prevent you from a closer look at this powerful synthesis language that you will not much use during the practical sessions. Thousands of references on the net, this link Syntaxe VHDL will still be sufficient for your developments.

The choice between code or schematic is not exclusive, and sometimes it is preferable to have a structural view of a part of the circuit and therefore adapted to the schematic view, sometimes we want to express behavior and "algorithmic" vision is then prefered. In your sessions, we will promote maximum schematic view which is very intuitive and does not require learning VHDL as such, even though the rigor that must be exercised in the graphical assembly is sometimes difficult. But "it is by designing one becomes a designer"

Creating a new project

To begin the design, create a new project with File> New Project. When you specify the project name and directory, avoid spaces in the path, I chose TP1.

Figure 2 Creating project TP1

The next step is to specify the type of FPGA you are targeting. For us it is one of the Nexys2 card (1200) or that of Nexys3 board.

Figure 3 Characteristics of Nexys2 board

Figure 4 Characteristics of Nexys3 board

Finally, Next and then Finish will complete this part.

Include a source in the project

To describe the system, you should add a new file to your project. This file will contain the circuit diagram that you define. So here you select Project> New Source ... and complete the dialog box allowing the tool to create a new file toplevel.sch by selecting Schematic and therefore the toplevel name.

Figure 5 Creating a schematic

By clicking Next and Finish you create the file toplevel.sch and ISE opens then the schematic design window for this file. You will soon understand that ISE is able to open multiple windows and that we can move from one to another using the tabs associated with each name. The logo

appears before toplevel.sch and indicates the root of your project.

Circuit entry

The main entry buttons (the same actions can be accessed by the Add menu) allow you to manipulate symbols, wires, buses.

Circuit construction can begin. The first step is simple, you will connect the 8 switches to the 8 LEDs on the board. No logic is required, it is as if you realize "welding" wires between the switches and the LEDs using ISE. While simplistic, it's still an architecture that will be programmed!

Therefore you will place in your toplevel diagram an ibuf8 and an obuf8 (these are buffers needed for input / output map). By clicking on the button Add Symbol, a list of available symbols appears. Choose from the IO sub-list both symbols mentioned above. Click on the name in the list and click again in the associated diagram to create an instance. (Ctrl Z to undo an action)

If you need to know what does a symbol, simply select it and click Symbol Info.

Figure 6 Creating a symbol

Add 3 wires (Figure 8) by selecting the appropriate button Add Wire and clicking on the location of one end and then clicking on the location of the other end. CAUTION you must be careful that the wire is well connected to the component, do not hesitate to zoom in to better view, all 4 small squares under the cursor which ensure good connection when the cursor is over the component gate. Add two I/O Markers at the two free ends of your wires, again selecting the right button and clicking on the two free ends. You still have to rename the 2 I/O Markers. Just select the wires one after one connected to the two I/O Markers. Use the Add Net Name button. Just name the inputs switches(7:0) and the outputs led (7:0). Once the name is entered, place it in the diagram by clicking on the concerned wire.

Figure 7 Naming wires and buses

Here are the results of your design, you should save your project. Effortlessly you created a circuit that consists of 8 wires associating each switches(i) to led(i) of your board. This set of 8 wires is called a BUS, the representation in ISE is the name notation (Upper:Lower).

Figure 8 Your toplevel.sch

Note: To make your life easier, ISE inserts iobuf by default. Here they are explicit because they allow you to specify two different names for the two I/O Markers.

You used logical names chosen by yourself (under my influence) for your wires and I/O Markers. To make ISE able to associate these logical names to physical names of pins on your programmable chip, you must explicitly give all the matches:

logic name = physical name

To do this, you must create a new source of type Implementation Constraints File (.ucf). This will be done by Project> New Source too.

Figure 9 The S3.ucf file creation

Next and Finish as always create the file and ISE opens the editor on this file for update. Here we must insert the code that corresponds to the Nexys2 or Nexys3 board as each board features a different FPGA.

UCF for Nexys2

Here are the pin names of the Sartan3E and their connections on the board.

Figure 10 The pins of the Nexys2 board- Digilent document

Here is the corresponding code to insert and save in the S3.ucf file.

The S3.ucf ​​file also appears in the toplevel.sch hierarchy.

UCF for Nexys3

Here are the names of the Spartan6 pins and their connections on the board.

Figure 11 The pins of the Nexys3 board- Digilent document

Here is the corresponding code to insert and save in the S3.ucf file.

The S3.ucf ​​file also appears in the toplevel.sch hierarchy.

Design compilation

There is not much to simulate for this example, however, you can test the circuit on the board directly!

ISE offers a simulation mode and an implementation mode. You must choose implementation inside the design tab.

Figure 12 compilation chain

This is the easiest part! It's ISE that will do the job. Nevertheless, you must support it with a set of information in order to get the job done.

You only still have to set the clock mode used when loading the FPGA. Select toplevel.sch then in the Processes window, right-click on Generate Programming File and from the drop menu click on Process Properties. Position the FPGA Start-Up Clock to JTAG Clock in Startup Options. For each new project you will certainly need to check this setting on the first compilation. You can generate the toplevel.bit file with a double click on Generate Programming File.

Figure 13 JTAG Option

When the compilation is successful, you have to load the produced code on the board. This one must be connected and turned on. You are going to use the Adept software supplied by Digilent.

Loading under windows

The generated file is in your project and is called here toplevel.bit. Run Adept from the start menu of your PC. Simply select the correct file with Browse and once it is done you can load the code produced by the ISE to the FPGA on the Nexys board. Click Program.

Figure 14 Loading to Nexys2 under Windows

Figure 15 Loading to Nexys3 under Windows

Loading under linux:

For Linus the design loading to the FPGA is done using the command line. Make sure your FPGA board is plugged in and turned on. Open a terminal, only two commands are used.

1. djtgcfg enum : This command will list all boards connected to the computer.
2. djtgcfg -d Nexys2 prog -i 0 -f toplevel.bit : This command loads the file on the Nexys2 board.

You can now check if the switches activate the corresponding LEDs.

The 7-segment display

We can continue to develop this project by adding a new feature. You will display the hexadecimal value represented by the 4 switches (3: 0) on the rightmost display among the available four displays.

You need to create a logic circuit that will transform a value coded on 4 wires to a 7 wires output, each turning on or turning off one of the 7 segments to get a visual representation of its value in hexadecimal (b0000 = x0, b0001=x1, b0010= x2, …, b1110 = xE, b1111=xF). It is a combinational circuit, we will see in future lessons how to implement this kind of circuits in ISE ... Rather, I suggest you use the VHDL language to define the behavior of your circuit and therefore specify what you want to transform rather than how you will transform. ISE will manage to generate for you, the necessary circuits to carry out the behavior.

Add a new source to your project. You already know how to do that. This time choose to create a VHDL Module. I suggest x7seg as a name.

Figure 16 Creation of the VHDL x7seg file

By clicking Next, you will be prompted to enter the ports of your new module. This is optional but it saves you the manual entry of this VHDL code part . Complete it or not, the resulting text file is completely alterable later. Enter the ports that will be inserted into the header of your VHDL file. The component converts the 4-bit input to generate a combination of the 7-segment output to display the numbers x0 to xF. In addition, insert the anode port to be used to enable / disable each of the 4 individual displays. This is the port that will choose the rightmost display from the available four displays. The direction of the ports must also be specified IN (input) or OUT (output).

Figure 17 Creation of the ports

Next and Finish automatically generate the skeleton of the VHDL x7seg.vhd module. ISE opens its text editor, it contains this skeleton. You may notice that x7seg.vhd is not yet included in toplevel.sch hierarchy. Correct, there is still no instantiation of this component!

The VHDL code is composed of two parts: the part ENTITY which includes the ports that you specified during the creation of this VHDL module and the ARCHITECTURE part that specifies the behavior. The VHDL syntax is clear enough to understand. It is this second part which is currently empty that needs to be coded. Insert this behavior between the ARCHITECTURE’s BEGIN and END.

For each value on the port sw(3: 0), we must clarify the segments to display on the output port sevenseg (6:0). To do this a WITH SELECT is used. The notation x"0" represents a number of 4-bit hexadecimal. The <= sign connects the value of the output signal to the value present on the input signal at a particular time. Intuitively, the signals are not variables stored in memory but rather values ​​that run on the wires and evolve over time ... No need to learn more for now.

Here is the code on 7 bits of your Nexys display, "1" for OFF and 0 for ON, so there is 7 wires to drive 7 segments (G F E D C B A), for example b1111001 lights B and C. The four anodes wires are used to select one or more of the four displays, here we choose the rightmost display by setting anodes to b1110.

Figure 18 The 7-segment display - from the Digilent document

Here is the corresponding VHDL code:

After inserting the VHDL code between BEGIN ... END, save the file, select it and check the syntax by clicking Check Syntax in the Processes window. It should be good. You will then be able to generate a symbol for that component which will then be instantiated in your toplevel circuit. Continuing in the same Processes window, open the hierarchy Design Utilities and launch Create Schematic Symbol.

Figure 19 Creating a symbol for x7seg

Back to the window associated to toplevel.sch, you can add the created symbol. Simply select the Add Symbol button, this time among the first lines appear your personal library symbols. Open the library and select x7seg by a double-click you add an instance in your toplevel circuit.

Figure 20 Inserting a personal symbol

Once x7seg placed in your schematic you must add wires to its outputs. Place two I/O Markers on the outputs. Rename them by renaming the corresponding wires sevenseg(6:0) and anodes(3:0). Before connecting the input port, rename the bus between IBUF8 and OBUF8 with the name data(7:0).

Figure 21 instantiation of the x7seg component

You still have to connect the 4 wires of data (3:0) to the sw(3:0) port. There is a special button to add a connection to a bus (Bus Tap).

• Click this button and the associated window appears, you can choose the direction of the connector, here Top seems adequate.
• Then click once on the bus on which you want to connect, here data(7:0). In the window the name data(7:0) appears, in this window you must now specify the wires you actually want to select.
• Change Net Name from data(7) to data(3:0).
• The only thing still to be done is to place your Bus Tap on the port you want to connect,

Here the port is connected to sw(3:0). Again here, you have to be careful about the connection and if necessary zoom in to see the 4 squares on the endpoint of your Bus Tap.

Figure 22 Bus Tap Initialization

Here is the end result of your design! Once the schematic toplevel is saved, the x7seg component appears in the its hierarchy because an instance of this component was placed there.

Figure 23 final Toplevel

You have added two I/O Markers (without iobuf that will be added automatically by ISE), they must be taken into account in the S3.ucf ​​file. You will update this file by adding the commands corresponding to the pins of your Nexys2 (Figure 10) or Nexys3 (Figure 11) board:

UCF for Nexys2 card

UCF for Nexys3 card

Ready for the synthesis!! Recompile all by Generate Programming File on toplevel.sch. Finally reload the toplevel.bit using Adept for a test on the board. You should see the value entered using the first 4 switches on the LEDs and on the first 7-segment display.

Your turn now

Question 1 : Print the switch value on the 4 displays simultaneously.

It's the anodes that drive the 4 displays. The VHDL code must be modified. When changing the ARCHITECTURE of a personal symbol, it is not useful to change the schematics that use it. On the other hand, if we modify the number of ports (ENTITY), ISE will ask you to update your schematic on this old symbol by clicking on the diagram or by opening the diagram in the editor. It is your turn now to add or remove the necessary wires.

ISE propose a command to update all the symbols in schematic files.Select the project and then Design Utilities with the command Update All Schematic Files.

Question 2: Make a display that turn on one single segment over the 7 depending on the number entered on the first 3 switches: display A if switch = 1, B for 2, etc …

Here too the VHDL code must be modified.

Question 3: Build the circuit that turns on the segments A, B ... G, for all combinations of the first 7 switches of the board. Example by setting switches 0 and 1, the segments A and B light on. We can avoid to use the x7seg component ...

Question 4: To complete question 2, use at the same time 4 remaining left switches to select which display will show the entered value specify on the first three right switches.

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