Lesson 4: 16-bit Display

In this lab, you will use ISE to build sequential circuits, simulate and execute them on the board. You will see how to assemble D latches to achieve clocked counters. You will see how we can slow down the system clock using such counters. The implementation will allow you to perform a complete sequential circuit, which will serve in the construction of your S3 processor.

The sequential circuits are essential to all processors. They allow to introduce the notion of time and duration in a digital circuit. This notion of time exists by the very nature of technological support: passing through an AND gate or an inverter takes time. Signals are thus related to timed events and their value depends on the concerned instant. Programmable circuits are effective when they are synchronously programmed, that is to say when the response time of a combinational circuit can be limited to a particular technology. We can then ensure that after a time equal to or greater than this limit the result of all outputs of the circuit is correct and usable by another combinational circuit. A periodic signal, called Clock, allows us to clock a complex logic circuitry ensuring that inputs at time t correspond to the outputs produced since time t-1. Again the choice of the clock period depends on the chosen technology and the maximum bounds of all circuits.

Required Knowledge

Sequential logic, switches, multiplexers, counters.

Objectives

In this lab, you will use ISE to build sequential circuits, simulate and execute them on the board. You will see how to assemble D latches to achieve clocked counters. You will see how we can slow the system clock using such counters. The implementation will allow you to perform a complete sequential circuit, which will serve in the construction of your S3 processor.

The project

In a first step, you will build a modulo 4 counter using two D flip flops. You'll see how to use the clock of the board to automatically increment this counter over time. Then you will build a display of 16-bit words on the four 7-segment displays. As we observed in Lesson 1, it will take four successive phases, each 4 bits of the word displayed on a different display, the technique is to play with the value of anodes(3:0) to successively scan these 4 displays fast enough that the eye can not perceive scanning.

D flip-flop and counter

As usual I suggest you create a new project TP4. Then create a New Source of type Schematic named toplevel. Once the file is created make it a habit to update immediately the properties: Remember that related to UCF file and allows the unused constraints and that related to the start with the JTAG option. All this becomes automatic and I will spare you from the ISE screenshots. If necessary re-read the previous lessons. In the following we return back to toplevel …

The D flip-flop

The D flip-flop used operates on the rising edge of the clock, that is to say the change in the output Q takes place at the time the clock goes from 0 to 1. It is only at this moment that the output takes the value of the input. Between two successive fronts the input value can change without affecting the output. We will use this period to change the value of D. If we reverse the output Q to reconnect it to the input D, there will be a cyclical change in the output Q which will be inverted at each rising edge of the clock.

Add a New Source named compteur4 of type Schematic. In this diagram instantiate a component fd, it is classified in the library flip-flop. You can (should) always read the Symbol Info. Add an inverter inv that must be returned: when creating click on rotate 180 or by right clicking Symbol> Mirror or the Mirror button. This inverter receives the output Q and the produces the input of your D flip-flop. Add then a clk wire on input C and a Q wire with both I/O Markers. You've no doubt noticed, ISE uses default names for all instances, wires etc. By double clicking the icon, you can change the name, it is useful when navigating in the simulation. Name the flip-flop BasculeD_0. You will already try to simulate this circuit!

French touch

compteur = counter

bascule = flip flop

Figure 48 fd flip-flop

As with the previous lesson, create a new source of type VHDL Test Bench and name it compteur4_tb. Choose compteur4 as associated source.

Figure 49 Creating test_bench for compteur4

You will modify the process of compteur4_tb file so that the clock is functional. The clock must be set to 0 and change state every 10 ns (ie a frequency of 50 MHz). Just change the following two parts of the code.

Place yourself in simulation mode and run Isim on compteur4_tb. You can observe the clk signal that is generated by your test_bench. The signal q is also periodic, it changes state at each rising edge of the clock. Note that the frequency of q is two times less than that of clk! This property is particularly interesting to realize our counter.

Figure 50 bascule D simulation

2-bit counter modulo 4

A counter that counts from 0 to 3 requires two binary flip-flops, one for each bit: b00 b01 b10 and b11. If we look at the sequence of values ​​produced at each top, we obtain:

By analyzing line by line, we see that Q0 changes its value at every incrementation while Q1 changes its value twice as slow and always when Q0 goes from 1 to 0. For Q0 you have just simulated the circuit with one D flip-flop. Q1 simply uses a second D flip-flop but instead of being clocked by the clock, it is with the reverse of the signal Q of the first flip-flop (Q0 when going from 1 to 0) that the second flip-flop is clocked. Let’s go! On the diagram compteur4.sch, remove the wire at the output of the flip-flop and its I/O Marker. Select the flip-flop with the inverter and the connecting wire. By copying and pasting (CTRL C CTRL V) you get a second instance of the D flip-flop. Name this instance by double-clicking basculeD_1.

Place a bus down horizontally and name it q (1:0). Place a Bus Tap between q (1) and the output q of basculeD_1, place a Bus Tap between q(0) and the output q of basculeD_0. Connect both produced wires with the corresponding inverters inputs . Place an I/O Marker on the bus q (1:0). Finally the output of the inverter associated with basculeD_0 must be connected to the clock C input of the second.

Figure 51 Counter modulo 4

Before you can simulate this circuit, it is necessary to update the compteur4_tb.vhd files. Indeed ports have been changed. The q output is now a bus Q(1 0). (Vhdl does not distinguish uppercase and lowercase!) Here are the modifications.

Once the simulation is launched. You must obtain the behavior of our modulo 4 counter.

Figure 52 Simulation of the modulo 4 counter

Go for the test on the board. You will generate a symbol for compteur4. In toplevel instantiate this component. Add an input wire named clk, a bus output appointed led(1:0) with their I/O Markers. On the board, you will see the counter values ​​on the first two LEDs. Import by a Project> Add Copy of the Source the file S3.ucf from Lesson 3. It contains the two LEDs. We must add the clk signal with the following command.

Nexys2 card

Nexys3 card

Generate and load the file toplevel.bit by Adept. Not much to watch !!! Both LEDs are always on. What is going on?

• Nexys2 board: The board clock is 50Mhz, so the signal q (0) value changes with a frequency of 25 MHz and q (1) with 12.5 Mhz.
• Nexys3 board: The board clock is 100MHz, so the signal q (0) value changes with a frequency of 50 MHz and q (1) with 25 Mhz.

Impossible for the eyes to see the changes. We are here on several tens of million changes per second. You need to slow the clock! You got the idea: a D flip-flop divides the frequency by 2. I suggest you build a clock divider with D flip-flops. This can be done relatively quickly with copy and paste! Add a New Source of type Schematic named ClkDiv. Place an instance of the D flip-flop using the fd symbol. Also instantiate a mirrored inverter. Connect Q to the input of INV and D to the output.

Select the whole with a first copy and paste and you will get two flip-flops. Connect the output Q of the first to the C input of the second. Here it is not a counter and the order matters little, it is better to go through as minimum gates as possible, we avoid an inverter between every flip-flop. By a series of copy and paste, create a line of seven flip-flops. Place connections between the outputs Q and the inputs C. By copy and paste create again three lines of flip-flops, you can delete the last two for Nexys2 and the last one for Nexys3. Add again the missing connections. On the input C of the first flip-flop place a wire named clk with its I/O Marker. Two flip-flops will particularly interest us:

• Nexys2 board: the 18th and the 26th,
• Nexys3 board: the 19th and the 27th.

Pull two wires from the outputs of these flip-flops, name them clk190 and clksec and add two I/O Marker. Clk190 frequency is around 190 Hz, it will be useful later. Clksec period is about 1.3 seconds. That is this one you use to clock your counter. We obtain the following circuit.

Figure 53a A clock divider for Nexys2

Figure 53a A clock divider for Nexys3

Next create the symbol and place it in toplevel between the I/O Marker and your counter. Use the clksec output to clock your counter to observe the changes on your leds about every second. This construction of clkdiv leads to clock shifts that can be troublesome for some developments. This is not the case here because the signals produced are used exclusively for the I / Os of the boards. Another building is proposed as an exercise at the end of this lesson.

Figure 54 Toplevel for the slowed compteur4

Your compteur4 is functional. You will be able to use it to achieve the four successive displays on your display material. To do that you need a 4 input multiplexer. It allows you to choose depending on the value of your counter which display to use and therefore what value to send on anodes, another multiplexer will allow you at the same time to define what part of the 16-bit word (4x4) to display on this 7 segment display.

This multiplexer must receive 4x4 input bits, two selection bits (from 0 to 3) and produce four output bits. Such a multiplexer does not exist in the ISE library. You're going to build it yourself.

Create a new source of Schematic Type named Mux4x4. Place 4 vertical buses with their I/O Markers appointed I0 (3:0), I1 (3:0), I2 (3:0), I3 (3:0) (use copy and paste once the first is realized, then simply change the default name). Place 4 instances of M4_1E that you find in the library mux. Place a bus on the left named O(3:0) that will be your output. Place a bus up horizontally named s(1:0) which will be your selector. You still have to connect a Bus Tap to the input and then to the output respecting precisely the indexes. For the first bus I0, select the bus and then connect the 4 Bus Tap to the four M4_1E on the D0 input, it is better to start with the index 3 because ISE decrements it for you automatically. Do the same for the other buses I1 on D1, I2 on D2 and I3 on D3. Connect the E inputs to VCC (symbol in General Library). Finally with 2 Bus Tap connect the wire s(0) to the S0 of the 4 M4_1E s and wire s(1) to the S1. Connect the four outputs of the M4_1E to the bus O(3:0) by 4 Bus Tap respecting the same order of the indices. You still need two I/O Marker s(1:0) and O(3:0). You should get the following circuit. You can simulate some test sets by hand as before using Force Constant in Isim. Finally create the symbol.

Figure 55 4x4 Multiplexer

You have already realized a 7-segment display during the TP1, you can by Project> Add Copy of Source add the code X7seg.vhd that should be in your project TP1. This is the original version of the code, not those of the questions asked at the end of TP. This component has already been tested, you can now create the corresponding symbol.

French touch

Afficheur16 = Display 16

You can create a component afficheur16 that will be reused for your S3 processor. Add a New Source of type Schematic and name it afficheur16. Place a compteur4. Compteur4 input is connected to an I/O Marker named clk. You will also instantiate two mux4x4 one under the other to the right of compteur4. Place an x7seg to the right of the first mux4x4 and connect the output of the mux4x4 to the input of x7seg: it is the digit that will be displayed. You can add a bus to the x7seg output on sevenseg (6:0) by giving it the same name and placing there an I/O marker (you will not use the output of anodes of x7seg which is fixed to b1110 in the X7seg code that you have got). On the second mux4x4 connect an output bus and name it anodes(3:0), with its I/O Marker. You still have to feed your two multiplexers. Before the first place to the left a vertical bus called data(15:0) with its I/O Marker. To select successively the 4 digits to display, with 4 Bus Tap connect data (3:0) to I0, data (7:4) to I1, data (11:8) and to I2 and data (1512) to I3 . You can then connect the output of your compteur4 to the input s(1:0) for each multiplexer. It is the same cyclic selection for both multiplexers. On the second multiplexer, you will add as input the four constant values b1110, b1011, b1101 and b0111 to select the correct digit for each increment of compteur4. You have already built constants (Figure 37, Figure 38). For the first constant add a constant symbol (in general) directly on the I0 port. Change its value by double clicking on it to b1110 and confirm, then again double click on the constant, for this time select cValue and by edit traits change its size to 4 and its radix to 2. With a copy and 3 pastes do the same for ports I1 I2 and I3. It will be sufficient to change the value for each copy.

Figure 56 4 bits constant

Figure 57 Afficheur 16 bits

You can simulate afficheur16. As always, you have to add a test bench afficheur16_tb. The VHDL code is essentially the same, we must generate the clk signal, and add an initial value to the bus data(15:0). I suggest you display the x1234 value.

Observe during the simulation the successive values of sevenseg and anodes. They must match the display of 4, 3, 2, 1 from left to right.

You still have to validate the lab on the board. Returning to toplevel, instantiate an afficheur16 and ClkDiv. You must use the clk190 output as input to the display, which corresponds to the specifications of your equipment. Add a wire clk at the input of ClkDiv and two buses sevenseg and anodes to the output of afficheur16 with their I/O Marker. You still have to place a data as an input. Place a bus data(15:0) as input to your afficheur16. The voard has only eight switches, I suggest you display this byte on the display followed by x00: if you put x24 on the switches, you will display X2400. Create a bus switches(7:0) with its I/O Marker, place an instance of Ibuf8 and as output there place a bus. You can then place a Bus Tap between this bus and data(15:8). A second Bus Tap between data(7:0) and the constant x00 finalizing the design of your circuit. Check before compiling that toplevel is the root of your project.

Figure 58 Toplevel to test your display

Your turn

Question 1

I suggest you re-analyse ClkDiv. It is possible to use directly the counters provided by ISE. Particularly the CB16CE counter which is a 16-bit counter that can be cascaded: Using two CB16CE components you can build a 32-bit counter. Then it will be sufficient to output both wires associated with the 18th and 26th bits for Nexys2 or the 19th and 27th for Nexys3. I will guide you in the construction of this new diagram testclk.

French touch

Poids forts = most significant

1. Place two instances of CB16CE that can be found in the library counter. Feel free to read Symbol Info!
2. Connect the two inputs C to the same wire clk with its I/O Marker.
3. Connect the first CE to Vcc, this counter is always active.
4. Connect the two CLR to Gnd, The counters will never be reset.
5. Connect the CEO output of the first counter to the CE input of the second. This constructs the cascade: the second will be active only when the 16-bit output of the first are '1'. At this time the 16 most significant bits are incremented by 1!
6. Place a bus at the Q output of the second counter you can name it poids_forts.
7. Add two Bus Taps on wires 1 and 9 on this bus for Nexys2 board and 2 and 10 for Nexys3 board (different frequencies).
8. Not being able to place a direct I/O Marker on a wire from a bus add a buffer symbol BUF on both wires poids_forts(1) and poids_forts(9) for Nexys2 and poids_forts(2) and poids_forts(10) for Nexys3. .
9. Finally create the two wires from BUF, name them clksec and clk190.
10. Place your I/O Marker on both wires.
11. Replace ClkDiv with this new symbol testclk in toplevel for a test.

Question 2

Go back to TP3 with your 4-bit adder and display the results on your afficheur16 using the first two digits for the result on 5 bits.

Answers

Curious …

Another implementation of a 7-segment display without clk190!

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