Lesson 5: FSM

In this lab, we will use ISE to build a simple controller.We'll use VHDL to develop this controller. As you will see, it is possible to define an FSM skeleton in VHDL. By separating to the best the FSM concept , the difficulty is of the same order of TP1 where it was required to develop in VHDL a process for signal conversion. In this skeleton, you will certainly need to include your contributions to achieve the behaviors supported by your controller which are mainly to schedule the system: to produce output signals and advance in the automaton. You will verify by simulation and by implementation on the board that the behavior of your controller matches your specifications. What you learn here will be reused later to build the control unit of your S3 processor.

FSM programming in VHDL

The best way to represent a clocked behavior is to use an FSM (Finite State Machine). This FSM is used to define what signals was needed to trigger at every moment and this depending on the context in which it operates. The realization of a FSM can be schematic and you have already done that for the realization of the 4-digit display. The use of a state counter followed by multiplexers with flip-flop to memorize the current state allows to produce such a circuit. However, for a significant FSM, we certainly need many components. I think VHDL programming is more readable and maintainable in this case. That is why I propose in this session an implementation in VHDL. This is the "VHDL" lesson in this set. I will once again guide you to simply use the VHDL features which compose then a language accessible to any programmer.

knowledge Requirements

Automata, FSM, programming basics.

Objectifs

In this lab, we will use ISE to build a simple controller.We'll use VHDL to develop this controller. As you will see, it is possible to define an FSM skeleton in VHDL. By separating to the best the FSM concept , the difficulty is of the same order of TP1 where it was required to develop in VHDL a process for signal conversion. In this skeleton, you will certainly need to include your contributions to achieve the behaviors supported by your controller which are mainly to schedule the system: to produce output signals and advance in the automaton. You will verify by simulation and by implementation on the board that the behavior of your controller matches your specifications. What you learn here will be reused later to build the control unit of your S3 processor.

The project

You have to design a traffic light management component and its symbol. You will use VHDL to develop this controller that would display the behavior on the LEDs, the 6 lamps of a crossing (2 x Red + Yellow + Green). Then you must instantiate the symbol in a diagram that integrates input / output which are the switches and LEDs of the board. Several levels of difficulty will be discussed.

A traffic light controller

Our specifications of the initial system are limited to a 4-state automaton for a cross crossing of two north-south (NS) and East-West (EW) streets. We define these four states as follows:

• Rouge_Vert (RV): Red on NS and Green on EW
• Rouge_Orange (RO): Red in NS and Yellow on EW
• Vert_Rouge (VR): Green on NS and Red on EW
• Orange_Rouge (OR): Yellow on NS and Red on EW

French touch

Rouge = Red

Orange = Yellow

Vert = Green

The FSM is also very simple, it is an infinite cyclic loop of 4 states. The system changes the current state at each clock tick and for each tick it lights the corresponding LEDs: the three right LEDs are led (2) => Red LED (1) => Yellow and LED (0) => green of a traffic direction. The three leftmost LEDs are LED(7) => Red LED (6) => Yellow and LED (5) => Green for the other direction. Here is a representation the FSM which positions the LEDs on each clock tick on the rising edge. The value of the LEDs is validated by the output of the corresponding state.

Figure 59 traffic lights automaton

You will create your new project TP5, insert a Schematic named toplevel and place both Properties for JTAG and UCF. Create then a New Source of type VHDL Module and give it the name fsm. ISE will guide you in defining the module. Here you need to create a clk signal input, this clock will allow the automaton to advance. There is no other input signal yet. However, you can also create a LED(7: 0) output port . Finally confirm creation.

Figure 60 Creating vhdl skeleton for the fsm

ISE opens the editor on the fsm.vhd file. The specification of the architecture is empty.

An FSM will consist of three circuits running in parallel. We called transition any change of state of our automaton.

• The circuit Next_node: will produce according to the current state and possible entries in the FSM, the next state (circles in your automaton) to which it will move during the next transition. This should correspond to the arrows on your automaton.
• Circuit Next_output: will produce according to the current state and possible entries in the FSM, internal signals to the FSM which we call xxx_i (xxx is the name of the corresponding output port) and representing the values to output at the next transition.
• Circuit Sync: allows to detect the rising edge of the clock and for each detection it generates actual output to the ports of FSM validating the internal signals produced by Next_output. It also changes the value of the current state based on the proposed next state by Next_node.

These three circuits are programmed in VHDL by three processes within the same architecture behavioral. The xxx_i internal signals must be defined locally for this architecture. Each process is limited to a sequential code mainly built with If Then Else and Case which are nothing else than multiple If as in all programming languages. The particularity of a process remains the sensitivity list. These are not the function parameters or other settings, these are a list of input signals to be observed by the process in order to respond to any changes in the value of one of these signals. Between two changes the circuit keeps exactly the same functionality as it keeps the same inputs. You will place in this list all ports of entry and internal signals of your FSM present in the predicates of your If or Case. The creation of an FSM is systematic as soon as the controller and ports are defined.

You can start editing your FSM for this traffic light control automaton.

1. Declare the internal signals corresponding to the output ports. Here, we must declare Led_i.

1. Declare next the names of your states (the nodes of the automaton). Using an enumerated type, ISE will transform these into binary words for you. Then declare the two states that will allow advancing in the automaton: state for the current state and next_state for the next state.

1. Let us start with the process Next_output. This process is sensitive to state: for each state must define the next LED output values according to the transition. You will create the process with State in the sensitivity list. Before anything else, all internal signals xxx_i should receive a default value, ISE will be able then to generate efficient code. Then the code is limited to a Case as a function of the current state: every time the state changes state the process changes the signal Led_i in respect of the specified automaton.

1. The second process will allow to predict the next active state of your automaton. Here again the process will be sensitive only to state signal, there is no input signal for now. This gives a process with the same style built around Case. The purpose of this process is to produce the value of next_state signal. Its behavior reproduces your automaton structure.

1. You still have the sync process. This one is only sensitive to the clock signal clk.It should detect the rising edge of clk and only then apply the change to current state and update the outputs from xxx_i internal signals .

You are able to start the simulation. You can add a new VHDL source of type Test Bench named fsm_tb. ISE will anticipate your work, it recognizes clk as a clock and will create the process that stimulates the signal. You still need here to comment the process stim_proc stimuli because only clk will be generated by the simulator. The obtained results validate the periodicity of the LED displays. You can create FSM symbol.

Figure 61 Simulation of the fsm

Go ahead and start the synthesis, you need thus to add to your project a copy of the S3.ucf file apudated during TP4, a copy of clkdiv.sch for which you will produce the symbol. Place in toplevel an instance of ClkDiv, an instance of fsm. Connect clksec to the input of your fsm. Place the two I/O Marker on the clk and LED(7: 0) ports. ISE will create for you directly both the wire and the bus and you need to rename them clk and LED(7: 0). The compilation can be started and then you can load the toplevel.bit on the card.

Figure 62 Toplevel tricolor

FSM with input

Figure 63 FSM tricolor with works

French touch

travaux = works

You will transform your fsm so that when the switches(0) is active, the lights go in works mode, i.e. Yellow flashing on both axes. As the timing constraints of the system are low, I suggest you go into works mode only when your automaton is in Rouge_Vert state. You must therefore transform your automaton by adding two new states Orange_on and Orange_off. The changes to your FSM are of several types:

1. Add an input port, I propose to name it travaux..

1. Add two new states in your type definition: Orange_on and Orange_off.

1. Change the process Next_node to realize your new automaton that takes into account this new input.

1. Edit Next_output so that Yellow flashes on both axes.

The simulation using fsm_tb does not work, because works was not defined before. I suggest you create a new source VHDL test bench named fsmtravaux_tb that will be associated to your new fsm. This time, you need to stimulate the signal travaux for a certain period of time. Simply add in the process Stim_proc the following code snippet:

The simulation is launched on fsmtravaux_tb. You will observe the following behavior.

Figure 64 fsm simulation with works

For the verification on the board you need to change toplevel. First of all you have to recreate the symbol associated with fsm by a Create a schematic symbol visible in implementation mode: the ports are not the same, there is now an input port travaux appearing. To update this symbol in toplevel, simply left-click on the page, you get the list of obsolete symbols with the ability to update it by clicking Update. Go for fsm. By reopening the window associated with toplevel, we get another screen to update outdated symbols of the same kind.

Figure 65 Updating obsolete symbols

Add a bus and its I / O Marker appointed switches(7: 0). Place a Bus Tap between switches(0) and the port travaux. It should be ready for compilation and execution on the board. It is your job now to test the behavior triggered by switches(0).

Figure 66 Toplevel fsm with works

FSM with inputs and outputs

We can always construct an FSM in which the separation between these three functions is fulfilled. The construction of the automaton remains the crucial point of the design, then it is not more than a translation work in VHDL. Moreover, some tools exist and can build it for you from a graphical interface of an fsm. Thus, I advise you to build if possible simple automata with the least possible states.

You will add to your automaton a new feature to your traffic lights. You are asked to have a time to display a green light 8 times longer on one axis. How to modify your automaton? You could add other 7 nodes: Vert_Rouge1 ... Vert_Rouge7. These are intermediate states inserted between Vert_Rouge and Orange_Rouge and would only be useful to pass the time. I propose instead to use a counter outside the fsm. It must be initialized to zero when the current state is Red-Orange via the activation of a reset_cpt output. The counter is incremented at each clock pulse indefinitely. Its output is an input signal taken into account by Next_node. It allows to switch to the next state Vert_Rouge when the value reached is 7.

Figure 67 FSM with a counter on an axe

If you want to keep a copy of the previous FSM, just do a File> Save As with the fsm_travaux.vhd name. Close the associated window and open that of fsm.vhd again. You will create a new source of type Schematic named controleur. I suggest you to instantiate a CB4CE counter that you will find in the library counter. Now we have to change the fsm.vhd file.

1. Add the new input and output ports here reset_cpt and cpt ports in the entity.

1. Add an internal signal for each new output signal, here for reset_cpt create the reset_cpt_i signal.

1. In Next_ouput process, you must initialize the new internal signal reset_cpt_i and place activations in the right nodes, here reset_cpt_i in Rouge_Orange state becomes active.

1. In the process Next_node you should consider changing your automaton behavior. As Cpt signal appears in the predicates of our process it must also appear in the sensitivity list.

1. In the process sync, you just have to accept the new output ports from the new internal signals.

You can then generate the symbol associated with FSM and place an instance in your controleur.sch scheme. The reset_cpt output must be connected to the input CLR (Clear) of CB4CE. Place bus at the input of Cpt and name it Cpt. with 4 Bus Taps connect the outputs Q3 Q2 Q1 Q0 to the wire of the same index of the bus Cpt (start by Q3 on Cpt (3)). The same clk wire is connected to C and clk of each component, place on it the I / O Marker. You also need an I/O Marker LED(7: 0) and travaux. Finally the input CE is forced to 1 by a Vcc symbol. You can create the controleur symbol for the future.

Figure 68 Controlleur with counter

For the simulation of your controller, create a file controleur_tb of type VHDL test bench. Just generate the clock clk to observe the behavior of our component. You have already done this in lesson 4.

Simulation allows you to understand why cpt is compared to the value 6 …

Figure 69 Simulation of the controler

Last step, you place a component controleur in toplevel instead of fsm. You can then test it on the board.

Figure 70 Toplevel with contrôleur

Your turn

Suggest a traffic light with 8 cycles on NS and 4 cycles on EO. One counter should be enough…

.