TriState

VHDL allows you to manipulate the third state '0', '1' and 'Z'. Even if the circuits do not support Tristate logic, ISE manages to simulate them with its own solutions. It is not doing so badly and the produced code is denser, faster than the one I proposed with connecteur16. This modification allows, among others, to execute unstable programs without need to reduce the clock frequency.

Here is the procedure to follow. Create a new source BUFT16 of type VHDL Module specifying as input a bus a(15: 0), a wire connect and as output a bus (15: 0). Just build the architecture by enabling the output to the input when connect = '1', otherwise the output is in state 'Z'.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity bufT16 is

Port ( a : in STD_LOGIC_VECTOR (15 downto 0);

connect : in STD_LOGIC;

b : out STD_LOGIC_VECTOR (15 downto 0));

end bufT16;

architecture Behavioral of bufT16 is

begin

b <= a when connect = '1' else (others =>'Z') ;

end Behavioral;

You can create the associated symbol. Then, you have to replace the 16 connecteur16 by this BUFT16 symbol. The cascade becomes a shared bus. The assumption of constant X0000 disappears with the constant. All control wires must of course be reconnected!