Here is the first step in the final construction of your S3 processor. S3 processor is a simple processor that will be feasible in the next 7 practical sessions. At the end of these sessions, you'll be able to run your own programs written in assembler S3 on Nexys board.

In this first step, you will discover the registry concept. You will be able to build a queue of registers sharing the same bus. You will end up performing a data transfer between one and several registers via this bus.

Block diagram of the S3 processor

Registers and registers transfer

Here is the first step in the final construction of your S3 processor. S3 processor is a simple processor that will be feasible in the next 7 practical sessions. At the end of these sessions, you'll be able to run your own programs written in assembler S3 on Nexys board.

In this first step, you will discover the registry concept. You will be able to build a queue of registers sharing the same bus. You will end up performing a data transfer between one and several registers via this bus.

knowledge Requirements

Registre, bus, automaton

Reminder

If you modify a component, it is necessary if it exists already to recreate the symbol and make updates in the upper levels that instantiate it!!! failing to do this, version 12.4 of ISE may not take into account the most internal changes.

Objective

In this first step, you will discover the registry concept. You will be able to build a file of registers sharing a bus. You will end up performing a data transfer between one and several registers via this bus.

The project

The S3 processor has 15 registers, an ALU, a control unit, an incrementer for CO, I / Os, a program memory and data memory. We will build step by step this processor by mixing a schematic entry and some VHDL code.

French touch

CO = PC

Compteur Ordinal =Pointer Count

As always this starts with the creation of a new project, TP6. You can immediately create the toplevel file in mode schematic and set the compiler options.

The registers

The file toplevel.sch is used to instantiate he future development of the S3 processor as well as all the components related to the Nexys2 or Nexys3 board. You will create a new source of schematic type called S3. The size of this diagram S3 once created should be increased for what you need, on the diagram right-click> Object Properties and you can choose the size A0P.

ISE symbol library already offers registers. Your could create yourselves from flipflops but it is easier to use the available symbol fd16ce.

I suggest you select this symbol in Flip_Flop and read its specification by Symbol Info.

Figure 71 The registre FD16CE of ISE

In fact these are 16 D flip-flops connected in parallel. The Dx inputs are copied on Qx outputs when CE = '1' and on the rising edge of the clock C. At any time you can reset Qx outputs to 0 by a CLR = '1'. Apart from these commands, Qx do not change and produce the desired memory effect.

You will use the CE input to trigger or not a write to these registers on the rising edge. I suggest you instantiate vertically in the middle of your schematic and in the following order, 15 registers. For each instance we will change the name of the instance (right click> Symbol> Rename ...). I advise you to align your instances, the tool helps you to do this in the Edit menu. (you can already take a look at Figure 76)

General registers: R1 R2 R3 R4 R5

I/O registers: Rled Rsw R7seg

ALU Registers: Rsrc1 Rsrc2 Rdest

Memory registers: Ram Rdm

Instruction load registers: CO RI

Figure 72 A name for each register

The registers are ready to be connected to the bus. Do not hesitate to save your schematics after each modification …

Bus and bus connector

The bus here is nothing more than a set of 16 wires that will allow the transfer one by one of the 16-bit words between the different registers of the processor. While it is possible to connect a bus to several destinations registers, it is forbidden to connect multiple outputs of different registers to the same bus. Indeed, if two registers were connected carelessly to the same wires there is no guarantee the value carried by this bus. ISE also would not be able to generate the corresponding circuit!

Figure 73 Not to do !!!

To share a bus between several producers one can use a 3 state logic: such a circuit allows under control of an enable signal to pass or not an input value to the output. If not validated the connection is not effective. Your FPGA does not support this kind of system it is necessary thus to combine with AND and OR gates. Our assumption is to allow only one register at a given clock period to position its value on the bus. This must be guaranteed thereafter.

First you will create a symbol that provides the connection to only one wire. Add a new schematic source in your project and name it connector. There will be three inputs R, Din and connect and one output Dout. The following function Dout = Din OR connect AND R allows you to realize the connection between the R input and Dout output when the input connect is active, otherwise the signal Din spreads on Dout. By placing Din of the first connector to 0 and with our initial hypothesis we can realize our bus cheaply.

In connector, simply place an AND and an OR gates. Then add the wires between the AND and OR gates. Add the I / O Markers naming them Din, connect, R and Dout. We obtain a circuit similar to the following.

1 bit connector

Maybe it is not useful to simulate as it is so simple ... You can create the connector symbol.

What you have done for a wire must be done for the 16 wires of the bus at the same time and with the same signal connect for the 16 connectors. Create a new source of schematic type connecteur16. It is necessary to place vertically 16 connector instances. To simulate it will be easier to name your instances C0 to C15. Place a bus of 16 wires named Din(15:0), a bus of 16 wires named R(15:0) and a wire connect vertically to the left and then a bus of 16 wires named Dout(15:0) vertically to the right of the 16 connectors. With Bus Taps you will be able to ventilate the 16 wires of each bus on the corresponding port of the associated connector. Start by Din(15), ISE automatically decrement the Bus Tap names for you. You have to carefully check your connections here, indices and bonds. Place to finish the 4 I / O Markers Din, R, connect and Dout. You can create the symbol when all connections are correct.

Figure 74 The connecteur16

Figure 75 Connecteur16 with a zoom on the first 3 connectors

To simulate this component, simply generate the corresponding test_bench connecteur16_tb by placing an initial value for Din, another value for R, initialize the connect signal to 0 and then set it to 1 after 100ns. In order to respect our hypothesis, we must also put to X0000 the Din input after 100 ns. You should make it alone this time.

You will be able to build the bus now. On the side (right) of each register place a connecteur16. Again I suggest you name them CR1, CR2 .... CCO, CRI. Then simply connect each output Q (15:0) of a register to the input R (15:0) of its connecteur16. The connect inputs for now are forced to 0 with GND. In cascade connect the output Dout to the input Din of the following connector. For the first Din, recpect our hypothesis! Thus, put a constant that you initialize in two steps to X0000 and to length 16 bits. Finally, the last output must be connected to the inputs of the registers. For now you will connect this output Dout CRI connector (spread the bus registers to leave a little space) with entries Rram, Rsrc2, Rsrc1, R7seg, Rled, R5, R4, R3, R2, R1. Rename this bus bus_data(15:0). For the other registers we will come back later.

All the registers are synchronous, you can immediately place a wire clk with its I / O Marker and connected to all C ports of the registers

Figure 76 The registres and the bus

Figure 77 Zoom on the 3 first registres

For this lesson, you will use the 3 I / O registers RLED, Rsw and R7seg. Regarding Rsw, the S3 processor being a 16-bit processor, the registers are also 16-bit. You will add a bus to the input of the Rsw register, name it switches(15:0) and add to it an I / O marker. For RLED and R7seg it is the output that must be recovered, add a connection to the output wire of each register to the left, name them LED(15:0) and D7seg(15:0) and place the I / O Markers.

Finally for the display on R7seg you will reuse components developed in Lesson 4. Therefore by Project> Add Copy of Source, insert clkdiv.sch and afficheur16.sch. If you built the testclk.sch in Lesson 4, you can use it instead of clkdiv.sch. The display is constructed from other components, it is also necessary that you add them: compteur4.sch, mux4x4.sch et X7seg.vhd. You can now recreate the two symbols associated with ClkDiv and afficheur16 for this project. In toplevel, simply place an instance of each component under S3, connect the input clk of ClkDiv to the already existing clk wire. Connect the clk190 to the display, connect the output D7seg(15:0) to the input of the display Data(15:0). Finally add to the two output ports a bus and I / O Marker named anodes(3:0) and sevenseg(6:0). This is exactly the same manipulation as lesson 4. (If your TP 4 has not been terminated, there is a version of these files at the bottom of the page, there are two clock generators that are functional)

To test your circuit, I suggest that you display on the LEDs and the 7-segment display, the positioned value on the board's switches. As there are only 8 switches and LEDs, we force the 8 most significant bits to x00. At each clock tick, we must load the Rsw register, open the bus output Rsw, load the RLED and R7seg registers. For that you will simply place a 1 in the entry of the three CE of the three registers to make them active. Place also a 1 on the connect input of CRsw connector to propagate its value on the bus. The final diagram should be similar to this one. At each clock tick, the Rsw register is updated while its previous value is copied to RLED and R7seg for display. We call this manipulation register transfer.

Figure 78 I/O Connections

Once all the connections are checked, you can create the S3 component symbol. Still only to place this symbol in S3 toplevel, name it mon_S3. For the port LED(15:0) of S3 processor, you will create a bus ld(15:0) and on the bus place a Bus Tap on ld(7:0) that you connect to OBUF8 from the IO library which produces the bus and its I / O Marker LED(7:0). For the input switches(15:0), connect a bus sw(15:0). Place 2 Bus Taps sw(7:0) and sw(15:8). On the first connect an IBUF8 connected itself to the bus and I / O Marker switches(7:0). The second Bus Tap is connected to a constant that you initialize in two phases: to the x00 value with a length of 8. For the clock, you're going to add as a preventive measure a BUFG from the Buffer library which improves the signal quality, Its output is connected to the S3 clk, on its input place a wire named clk with its I / O Marker.

Figure 79 Register transfer for toplevel

Simulation

This is roughly the same as Lesson 4. You will add a new VHDL source of type test bench associated with toplevel. In the VHDL code, just add the code to generate the clock to 50 MHz. You can also test your circuit with different values on switches(7:0) here x12. In simulation mode start Isim on toplevel_tb.

By adding on the simulation window the values q(15:0) of the registers RLED, Rsw and R7seg (just open the hierarchy in Isim to find the instances of the three registers, then drags the variable q (15:0) to the simulation window), you see the following behavior:

To observe a change on the anodes and sevenseg buses you will need to push the simulation to more than 5 ms, the frequency of the display being 190Hz. You will see then the second digit display. If you change the value of the switches with a frequency greater than 190 Hz, you may mix the display of the beginning of an entry with the end of the previous one. But changing switches by hand in less than 5 ms and successfully see on the display is not humanly possible …

Checking on the board

You will be able to run your S3 processor with this first register transfer function. As usual you must add the S3.ucf file to your project before generating the toplevel.bit file. After loading by Adept, you should see the input value of the switches on the leds and on the display the value "x00zz where zz is the hex value input on the 8 switches.

Once validated, you can copy your project to TP7 for the next lesson. Simply select File> Copy Project, choose the name TP7 and select Exclude files generated.

Figure 80 Copying a Project

Your turn

Question 1: Perform the display only on the LEDs.

Question 2: Make the display only on the 7-segment display.

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