Research activities

The major contributions and achievements of my research activities cover two separate topics:

modeling of circuit interconnects (during my graduation studies);
use of optical emission form CMOS transistors to study integrated circuits (work started during my Ph.D. at Politecnico di Milano and still continuing at IBM Research);

The second topic can be further subdivided into:

Hot-carrier emission characterization, modeling and simulation;
Instrument control, automation, and data analysis;
Light Emission from Off-State Leakage Current (LEOSLC) study;
Latchup study
Detector and tool improvements;
Novel applications of optical techniques to circuit testing and diagnostics.

Circuit interconnects modeling

As the circuit density increases, the propagation delay of interconnects limits the length of global routing. Software tools for the extraction of the interconnect capacitances become essential for a successful circuit design. Many efforts have been devoted to develop numerical methods to deal with the analysis of three-dimensional interconnect networks, such as methods based on the use of Green’s functions. However, despite interesting advances, the low efficiency of these approaches still hinders their use in standard design tools. In fact, commercial software for interconnect analysis relies on the use of analytical formulas derived from the study of simple topologies, such as the single or double metal line on a ground plane. Often these formulas have been the result of extensive numerical simulations and empirical corrections are then employed to account for the presence of insulating layers with different dielectric constants.

As an undergraduate student, from Nov’97 to July ’98, I decided to take over the task of developing new compact formulas for the capacitances of the most common 2D interconnect structures by using an innovative physically-based approach. The idea was to divide each 2D structure (e.g. the double line on a ground plane) in a suitable subset of more elementary components like horizontal and vertical plates. The capacitances of these elements have been rigorously derived by the conformal mapping method, that I was able to master in a very short time (two months) without prior experience in this area. Then each element was properly combined to build the capacitance of the original structure. The advantage of this approach is that the function giving the capacitance of each plate retains the correct dependencies on the geometric parameters of the line. Therefore very few 2D simulations were needed to tailor the coefficients of the final formulas, reaching accuracy better than previously reported results. The capacitances of structures composed by one, two or three lines on a ground plane are then written as a weighted sum of more elementary components. Since the elementary terms already account for the correct geometrical dependencies, very few numerical simulations have been required to tailor the formulas, attaining accuracy higher than previously known results, over a wide range of the geometrical parameters of the lines.

The new formula demonstrated an elevated accuracy if compared to the detailed 2D simulations of the structures studied, as well as a significant improvement compared to previously published state of the art formulas by Sakurai-Tamaru. In specific, on a broad range of structure sizes, the error for single interconnect line is <3%, while previous formulas were able to guarantee only <6%. More complicated effects such as interconnect cross talk strength and dielectric layers are modeled with an error less than 5%, while previous formulas were not able to reduce error limits below 10-15%.

The importance of the results of this work allowed me to:

graduate 100/100 summa cum laude in Electronic Engineering at Politecnico di Milano, Milan, Italy;
publish a widely accepted paper in the prestigious IEEE Trans. Electron Dev., 47, 222-231 (2000) titled “New formulas of interconnect capacitances based on results of conformal mapping method”;
become a reviewer of several papers on similar topics submitted to the IEEE Electron Dev. Lett. in the following years;
enter in contact with research groups in semiconductor industries such as STMicroelectronics, interested in incorporating the formulas in their layout tools.

Hot-carrier emission characterization, modeling and simulation

In the late ‘90s, the use of light emitted by switching transistors was becoming a very important method for testing and diagnosing integrated circuits, based on the Picosecond Imaging Circuit Analysis (PICA) technique invented in 1995 by Jim Tsang and Jeff Kash at IBM Research. In fact, this technique allows measuring signal propagation delays, skews, etc. in a non invasive fashion, anywhere inside the integrated circuit. However, it was becoming clear that emission intensity had a strongly non linear dependence from the circuit electrical parameters, such as the supply voltage. This was making it difficult to use emission measurements to explain certain failing mechanisms and also apply it to analog circuit characterization.

In 1998, during my Ph.D. at Politecnico di Milano, I decided to start working on the characterization and modeling of the emission from individual transistors, and its subsequent use for optical signal simulations of integrated circuits. The work was carried out in collaboration with external semiconductor companies, mainly IBM and STMicroelectronics, that where providing sample devices in the latest technology generation. The work was divided in three fundamental steps: hot-carrier emission characterization, modeling and subsequent use of the model in circuit simulations.

Emission characterization

Since at the time there were no optical characterization systems, the first step was to assemble one for measuring the light intensity emitted by individual devices in a controlled environment. The chip containing the individual transistors was mounted in an open package and wire bonded. The special open package was then mounted on a custom design electronic switch board that allowed for the selection of the different transistors to be measured and was also feeding the electrical voltages necessary to bias the device under test. An array of voltage source and current meters was mounted in a rack and connected to the board. The instruments were connected together through a communication bus (known as GPIB) to a computer that was able to control them, change the bias point of the transistor under test, acquire the measured electrical parameters of the experiment, and analyze the data. The board was mounted on a three axis positioning stage under a microscope. The microscope was modified to be compatible with different types of photodetectors such as Charge Couple Devices (CCD) and Avalanche Photo-Diodes (APD). Once a set of measurement set points was decided, the computer automatically stepped through them, biasing the device under test, reading the electrical parameters and subsequently acquiring a measurement of the emitted light intensity at that condition. A novel image filtering algorithm was also invented for CCD, based on the autocorrelation and differentiation process. The technique analyzed each pixel of the acquired image, eliminating narrow and isolated peaks due to cosmic rays. Once analyzed, the emission data was plotted as a function of any of the electrical parameters of the transistors, thus providing the experimental data for developing a model of the emission mechanism.

Preliminary results of this characterization work were presented for the first time and the European Solid-State Device Research Conference (ESSDERC) in 1999 with a paper titled “Non-invasive optical characterization technique for fast switching CMOS circuits”. This was the first international paper to address the need of characterizing the emission mechanism to be used for optical testing of integrated circuits.

Emission trends

After finishing the Ph.D. course and joining IBM Research, I have continued working on the characterization process on always newer technology generations with shorter channel length and lower supply voltage. Most of the activity has been formally included in a Joint Study Agreement between IBM Research and Politecnico di Milano under my supervision. The data collected on different transistor sizes for several technology generations has allowed us to better understand the trends of the emission intensity as a function device scaling. The results of this research, published in the paper “Characterization of backside hot-carrier luminescence in scaled CMOS technologies” at International Reliability Physics Symposium (IRPS) 2006, confirmed that the emission intensity does indeed exponentially decreases with the supply voltage for a given device in a specific technology node. However, the collected data allowed us to discover two important effects, never reported previously:

moving from one technology generation to the next, the intensity of the light emitted by the scaled devices jumps up;
the exponential decay of the emission as a function of the supply voltage tends to become less steep.

By combining this discovery with the knowledge of present photodetectors, we were able to conclude that optical testing of integrated circuits will remain an important diagnostic technique in the foreseeable future.

Compact model of emission

Soon after being invented, Picosecond Imaging Circuit Analysis became very effective in using time resolved emission from circuit to measure on-chip signal propagation delays and skews by detecting the light pulses emitted by switching gates. However, it was also apparent that in order to tackle problems in the analog design world and also to interpret more complicated emission waveforms, a model of the emission was necessary. The model was applied to several different failing hypotheses, comparing each simulated result with the measured optical waveforms of the failing circuit, until a good match was found: the corresponding failing hypothesis being the root cause of the problem.

In 1999, during my Ph.D. at Politecnico di Milano, I started working on an emission model that would be able to explain and fit the experimental data that was being gathered from individual transistors. Previous literature was theorizing an exponential dependence of the emission intensity from the supply voltage. However, no details were provided regarding other important electrical parameters of integrated transistors, such as the drain current, threshold voltage, etc. At that time I made a fundamental observation that experimental curves of the emission appeared very similar to the substrate current, caused by impact ionization in the transistor channel. Elaborating on the theory of impact ionization and substrate current, I was able to create a model for the light emission for when the transistor is in saturation. The intensity is proportional to the number of carriers accelerated along the transistor channel and the probability of photon emission for each carrier. The number of carrier is linearly proportional to the drain current while the emission probability has an exponential decay with the effective voltage across the pinch off region of the transistor, normalized to an effective voltage. The latter could be expressed as a function of technology parameters but it is often estimated by fitting experimental data.

This physical model:

is simple (a small set of equations);
explains very well all the experimental characterization of individual transistors;
was presented at the International Electron Device Meeting (IEDM) 1999 with a paper titled “Tools for non-invasive optical characterization of CMOS circuits”;
is the first ever published set of equations liking emission intensity to transistor electrical bias conditions;
is still used for interpreting emission waveforms from failing devices, notwithstanding continuous changes in silicon technology.

Optical simulation of integrated circuits

The most important application of the emission model, and also the reason why it was developed, is related to optical simulation of integrated circuits. During the design of a new circuit, before fabrication, the expected behavior and performance of the circuit is studied by means of simulation of the electrical characteristics (voltages and currents) of complex gates and individual transistors. Once the circuit is manufactured, simulations can be used as a benchmark and also to understand the root cause of performance discrepancies and failing conditions. This has been in used for a long time and has worked very well with the electrical testing of circuits. However, the adoption in 1995 of optical testing techniques, able to measure emission waveforms, required the simulation of expected light emission, in addition to the usual electrical waveforms. This can be achieved only by using an emission.

In 1999 and 2000, I worked on the development of several applications of the emission model as described in the previous paragraph. Most of the effort was concentrated in four major research areas:

the creation of a simple compact model to incorporate into simulation tools, such as SPICE, for real time simulation;
the creation of a post-processing tool to apply to already available electrical simulation;
the creation of averaged emission maps of the circuit to be compared to time-integrated emission measurements obtained with static imaging detector such as Charge Coupled Devices (CCDs);
the use of optical simulations for interpreting emission waveforms and find the root cause of circuits fails.

The development of the simple compact model to incorporate into simulation tools, such as SPICE, started in parallel with the characterization of the emission intensity. Several variations of the model have been created to adapt it to the different simulation environments that are typically found in the industry. In summary, the newly developed transistor model adds a new terminal at the common transistor part that can be found in SPICE. Since only voltages and currents can be interpreted by the simulation tools, the additional terminal (optical emission intensity terminal) produces a voltage signal that is proportional to the expected/simulated emission intensity from the transistor. The SPICE model wraps around the standard transistor model and uses the instantaneously simulated bias conditions of the transistor as input values for the emission equations. Since the emission model depends on, but does not affect electrical bias conditions, the simulation process is not slowed down by recursive equation solutions and it is hence very fast and efficient. This tool was applied to a simple test circuit: a CMOS ring oscillator. The preliminary results were presented for the first time at the European Solid-State Device Research Conference (ESSDERC) in 1999 with a paper titled “Non-invasive optical characterization technique for fast switching CMOS circuits”. This represented the first demonstration in the literature of optical simulation of integrated circuit using an emission model.

I used the post processing of electrical simulations to estimate emission waveforms several times in the last years to interpret optical waveforms and identify the root cause of failing circuits:

In my journal paper “Tools for contactless testing and simulation of CMOS circuits”, Microelectronic Reliability, vol. 41, no. 11, Nov. 2001, pp. 1801-1808, the emission model was used to estimate the input impedance of a receiving circuit from the interpretation of the discontinuities in its measured emission intensity. This was first time in the literature that the light emission from integrated circuits was used to estimate characteristics of the circuit, beside signal propagation delay and skew.
My conference paper “CMOS circuit analysis with luminescence measurements and simulations”, European Solid-State Device Research Conference (ESSDERC), 2002, represented the first study in the literature of an analog circuit by means of optical measurements. Simulated and measured emission waveforms were compared to estimate non ideal parasitic effects common in integrated circuits, such as capacitive loads and impedance. For the first time an analog quantity such the discharge constant of a capacitor was estimated by only optical measurements, without invasive electrical contacts.
In our conference paper “Backside flip-chip testing by means of high-bandwidth luminescence detection”, European Symposium on Reliability of Electron Devices (ESREF), 2003, optical simulations of an integrated circuit were used for the first time in the literature to identify the failing mechanism of the circuit under test. Several failing hypothesis were simulated until the once matching the measured emission intensity was found.

Instrument control, automation, and data analysis

In order to characterize the emission from individual devices, as well as test and diagnose integrated circuit, I have been continuously working on the development and improvement of many different experimental setups during the past years. I have been selecting and purchasing powers supplies, signal generators, voltage and current meters, collection optics, microscopes, photodetectors, cooling systems, etc. Instruments have been assembled into general purpose measurement systems, data acquisition systems quickly assembled for a specific project, as well as an addition/improvement of a commercially available tool.

Beside the hardware part, a very important component of data acquisition and elaboration is the software. In the past years, I have been developing instrument control software in several different programming languages commonly used in the industry (e.g., C/C++, LabWindows, MATLAB). Among others, the developed software related to:

full-featured stand-alone control panels for the remote control of individual hardware instruments;
integrated measurement applications requiring the coordination of many electrical and optical instruments for measuring complex circuits at many different conditions;
a remote shared environment for the cooperation of several team members from different remote working locations;
automated data filtering and analysis;
optical image resolution enhancement by using registration and restoration algorithms;
automated data logging and instrument control.

Light Emission from Off-State Leakage Current (LEOSLC) study

During my second internship experience at IBM Research in 2001, I had the chance to work on the development of a new area of applications of optical emission techniques, based on the detection of the Light Emission from Off-State Leakage Current (LEOSLC). Until then, the near-infrared light that was used for testing integrated circuits relied on hot-carrier emission due to the transistor carries in the channel being accelerated/energized by the longitudinal electrical field. In order to emit light, both current and intense electric field are required inside a given transistor, thus limiting the emission to the so called saturation region of the transistor characteristics. This condition is typically met by functional CMOS circuits only during the short time when the gates are switching their output state. In standby mode, the entire supply voltage drops across one of the transistors in the stack but there is not current flowing, i.e. no carriers to accelerate. This is the fundamental reason why CMOS transistors, invented in 1963, found an almost immediate application in low power ICs as an alternative to bipolar.

However, as a consequence of the continuous trend in transistor shrinking and threshold reduction, CMOS transistors started to slightly conduct, i.e. leak, in the off state, when the gate voltage is set to ground. In practice, the gate terminal starts to loose the full control of the channel that becomes more and more affected by the drain voltage until a leakage current is formed between drain and source. In recent generations of VLSI circuits, this leakage current is becoming larger and larger, thus creating significant problems for power consumption and chip cooling. On the other hand, associated with the leakage current there is a faint near infrared emission, called Light Emission from Off-State Leakage Current (LEOSLC), which has been observed for several years. The light emitted by sub micron transistors can be measured by means of photo-detectors such as Charge Coupled Device (CCD) cameras, Photo Multiplier Tubes (PMTs) or single point detectors such as the Superconducting Single Photon Detector (SSPD) and the InGaAs Avalanche Photo Diode (APD). Several ways to use the LEOSLC were devised for testing integrated circuits.

One important observation made at the time was that the intensity of LEOSLC is strictly correlated with the state of the gates in the circuit under test. For example, considering an inverter gate, the n-type transistor is emitting light every time the output is logic high, while the p-type transistor is emitting in the opposite state. This can then be used to map the logic state of a circuit by taking a time integrated image of its LEOSLC, as demonstrated in the paper titled “Optical diagnosis of excess IDDQ in low power CMOS circuits”, winner of the Best Paper Award at the European Symposium Reliability of Electron Devices (ESREF) in 2002. The same concept was later applied to the diagnostic of a scan chain fail as reported in the paper titled “Broken scan chain diagnostics based on time-integrated and time-dependent emission measurements” presented at the International Symposium for Testing and Failure Analysis (ISTFA) in 2004. The novel optical technique based on the LEOSLC made it very easy to locate the fault, later confirmed by Physical Failure Analysis (PFA), which eluded for long time attempts of localization based on different diagnostic techniques. In fact the fail was not on a latch along the scan chain, but on a clock buffer. This work saved IBM a lot of development time and money. Moreover, this paper, and several other papers from our group, clearly proved the power of this new methodology, which was quickly adopted in the industry with several following publications from other test and failure analysis labs.

The intensity of the LEOSLC is also an exponential function of both the gate and drain voltage applied to the transistor. This can be used in many different ways for characterizing circuits. For example, in the paper titled “Optical diagnosis of excess IDDQ in low power CMOS circuits”, European Symposium Reliability of Electron Devices (ESREF) 2002, we proposed and demonstrated for the first time in the literature that, by characterizing the dependence of LEOSLC from the supply voltage, one can extrapolate the voltage drop in the power distribution grid of a chip due to the finite resistance of the metal lines (usually called IR drop). In order to estimate the resistance of the power grid of the IC, one has to take a series of short time-integrated acquisitions from a reference (beacon) circuit/gate at different voltages with the circuit not operating (the LEOSLC is nevertheless sustained by leakage current). Then, the circuit is operated in normal condition and the LEOSLC from the beacon is characterized again as a function of the voltage. Theoretically, the two curves should exactly superimpose because they correspond to the same device in the same operating condition (i.e. disabled). However, a significant reduction of the intensity can be observed when the circuit is working. Such an effect can be directly attributed to the voltage drop on the power grid of the IC, caused by the large absorption of current, and can be used to compute the value of the resistance of the power grid. We were able to estimate very precisely the IR drop for the test structure reported in the paper and verify its accuracy by electrical measurements.

In more recent work, using a high-sensitivity detector with a very fast response time, I proposed a new technique for the estimation of switching noise components in VLSI circuits. The method combines the measurement of the LEOSLC from quiet device of a VLSI circuit and the use of Fast Fourier Transform (FFT). In the paper titled “Local probing of switching noise in VLSI chips using time resolved emission (TRE)” presented at the North Atlantic Test Workshop (NATW) in 2005, I have shown that the spectra of the LEOSLC gives an accurate representation of the components of the switching noise in the frequency domain. By changing the operating conditions of the chip, one can acquire a different spectral pattern of the emission and compare the relative amplitudes of the tones. This characterization can be used to study not only the on-chip power distribution grid but also the resonant frequency of the package.

Latchup study

In 2002 I started working as a Postdoc Researcher at IBM Research in Yorktown Heights, NY. Given my expertise with optical techniques as well as my knowledge of carrier generation and recombination processes in silicon, I was put in charge of a new task force created to investigate the possibility of tackling a long standing latchup problem by using optical investigation techniques.

Latchup is the ignition of the pnpn or npnp parasitic structure (also know as Silicon Controlled Rectifier (SCR) or thyristor) created in conventional bulk CMOS technologies by neighboring transistors of different type. Such a structure is composed by two npn and pnp bipolar transistors (one is a vertical or horizontal device, while the other is a lateral device formed in the substrate) closed in a positive feedback loop. During normal operating conditions the pnpn structure is characterized by very high impedance, and no significant current flows through the structure. However, carriers injected into the structure, or voltage variations, can turn on one of the two bipolar transistors, thus leading to significant self-sustained conduction between the supply voltage and ground, the so called “latchup”.

A new electrical and optical setup was quickly assembled in less then a week to study the latchup formation at the Input/Output (I/O) interface of IBM chips. The chip under test was mounted on a board connected to an external power supply providing the necessary operating voltage. After initializing the chip in its quiescent state, a current source was used to inject progressively larger amount of charge into an I/O pin to be tested, thus simulating electrostatic discharge taking place during hot-swap of boards in a real system in the field. When the injected current is high-enough, but still under the typical discharge limit that the circuit should be able to withstand in real applications, latchup may eventually form. During the test, the board is positioned under an emission microscope, collecting the emission light due to the carrier recombination processes from the area surrounding the I/O of interest. By means of this novel adaptation of the JEDEC78 testing procedure, an automated computer controlled latchup test program was developed. Emission microscopy was used to characterize the ignition and diffusion of latchup in a series of I/O pins of a test chip. Many different I/O environments were examined in order to evaluate latchup sensitivity in bulk technology for applications where I/Os can be subject to voltage spikes during operation.

The circuit structures and devices that are most prone to latchup were first localized and then identified. In particular, Unused Gate Arrays (UGAs) placed in the neighborhood of the I/O circuits are shown to be very susceptible to latchup, due to the characteristic bias of their source and drain diffusions. It was also demonstrated that the latchup in the UGA can act as a secondary source of minority carriers, leading to latchup in logic circuitry. A simple solution is to remove any UGA structure from around I/O circuitries and substitute it with NWSX contacts whenever possible. It was also shown that minority carriers can diffuse underneath lines of decoupling capacitances, if the recombination length of the minority carriers is comparable with the size of the capacitances. Although they are immune to latchup, decoupling capacitances cannot be used alone to slow down its propagation.

For the first time we were able to image the formation and propagation of latchup outside of I/O circuits. This enormously simplified the understanding of the physical processes involved and allowed for the definition of new design rules and circuit modifications that ruled out latchup problems for other IBM products. In particular, we required a higher density of substrate contacts as well as a more random or “grid-shaped” placement of the contacts instead of the standard bar structures. This new approach prevents the formation of unprotected areas and impedes any diffusion paths. The optimized design led to latchup robustness far exceeding industry requirements.

This new technique allowed IBM to dramatically reduce the time to market of high end product chips, reducing costs. I was awarded a Research Division Technical Award in 2003. A technique based on pulsed current injection was also developed: it allowed for the identification of two separate latchup conditions, one current controlled and one charge controlled. We proposed that, based on this information, the carrier recombination and generation constants can be estimated by using only optical means. Several papers describing the novel methodology were published in six international conferences. The technical community recognized the importance of this technique by requesting a couple of invited publications in international magazines and desk reference books.

The methodology that we developed in 2003 to study latchup ignition and propagation by using time-integrated emission measurements has been recently reported as "Stellari's animation methodology" in the book "Latchup" by S.H. Voldman (John Wiley, 2007). The author reports that the techniques allows for better visual understanding of the latch-up ignition with a greater time resolution compared to the standard JDEC78 technique. The latchup propagation phenomenon is controlled and studied by limiting the injection current and taking subsequent time integrated images of the emission due to carrier recombination. Additional results presented in our previous papers have also been reported.

Detector and tools improvements

During my Postdoc period at IBM from 2002 to 2004, I was also leading a second important project involving the development and evaluation of new tools and detectors to improve and extend the usability of the Picosecond Imaging Circuit Analysis (PICA). In fact, the continuous trend of the modern semiconductor industry towards smaller devices and lower supply voltages is causing significant changes in the intensity and spectrum of light emitted by present generation integrated circuits: the total detectable light decreases exponentially with the electric field in the transistor, and linearly with the lateral dimension of the transistor. In particular, the progressive shift of the spectral distribution of the emitted light towards longer wavelengths makes the use of the PICA technique based on the use of the conventional S 25 Photo-Multiplier Tube (PMT) more challenging, due to its lack of sensitivity in the near-infrared region of the spectrum.

The IBM patent on the Picosecond Imaging Circuit Analysis (PICA) technique had been recently licensed to a tool building company, NPTest (formerly Schlumberger). My task was to pursue a close collaboration with the tool company to work on two major aspects:

the improvement of the newly available commercial version of the PICA tool;
the evaluation of a new experimental detector based on superconducting materials with superior optical performances.

This was achieved by spending almost a month at NPTest research and development facility in San Jose, CA during the summer of 2002, as well as weekly technical meetings to discuss progress and initiatives.

When I joined IBM as a Postdoc, we had just received the first version of the new commercial tool. After a quick assessment in September 2002, we were very disappointed about the poor reliability of the tool that was not mature enough for a production environment. I therefore devised a plan to test and evaluate both hardware and software components of the tool by extensive usage during typical and atypical measurements. I was soon able to find tens of problems and bugs, prioritize them based on the severity of their effects on the tool usability and performance and feed back corrective actions to be taken by the tool vendor. By the spring of 2004, after several steps of improvements, we were finally able to have a tool stable enough to tackle and successfully solve several diagnostics problems affecting the high-end chip product line of IBM.

Almost at the same time a new experimental detector became available for the commercial PICA tool. Since our group was at the leading edge of PICA analysis, we obtained a prototype version of the detector to be evaluated for its use in real life diagnostic cases. The detector, invented at the Moscow Pedagogic University, consists of a narrow strip line of a superconducting material patterned a meander. Once the detector is cooled down to about 2 K, it becomes superconducting and a constant current flows through it without encountering any resistance. If the material is hit by a near infrared photon, a hot spot may be created, the superconductivity is broken and a voltage spike can be observed at the strip line ends by the front-end electronics. Maintaining the detector at such a low cryogenic temperature and effectively coupling the light from the emitting circuit to its active area is very challenging. Several improvements in the cold optics were devised, with progressively better efficiency and rejection of the background thermal noise due to the ambient. An efficiency of up to 7-8% was finally achieved. This, coupled with an almost negligible noise and a very high rate of photon detection, which made it very much useful for the type of measurements required by the PICA technique.

Through my research activity I was able to push the performance of the superconducting detector to a new limit. By carefully tuning the detector bias, tool optics, as well as cryogenic temperature, I was able to demonstrate world record low voltage measurements of signals inside integrated circuits:

down to 0.8 V in 130 nm technology node with the first prototype version of the detector;
down to 0.6 V in 65 nm technology node with the latest and improved version of the detector;

These results are still unmatched in the literature even by newer types of photodetectors, and will allow us to extend the use of the PICA technique for future CMOS technology nodes. Moreover, the paper reporting these results, titled “Testing of ultra low voltage VLSI chips using the Superconducting Single-Photon Detector (SSPD)”, earned the Best Paper Award at the European Symposium on Reliability of Electron Devices (ESREF) in 2004. Besides demonstrating for the first time the application of the PICA technique to chip running significantly below the nominal supply voltage, I was also able to present state of the art results in terms of time resolution and noise levels for the new detector.

The novel superconducting detector has been used extensively for the last three years and has helped diagnose more than a dozen critical problems on several IBM microprocessors. This was recognized by several IBM awards: Research Technical Award and two management Thanks Awards. The continuous work to advance the state of the art of optical testing has been published in several papers in international conference and journals, as well as patent applications aimed to the improvement of the tools and new application areas.

In the past years I have continued collaborating with other companies and research centers to improve the PICA tools and technique and make sure that it will continue to suit IBM needs for testing and diagnostics. New vendors have come to play in this arena, among them:

Credence Corp., with a new InGaAs based avalanche photodiode and a new PICA tool with additional capabilities such as laser based excitation techniques and more advanced cooling capabilities. Within this collaboration, I was in charge of performing a detailed analysis and comparison of the InGaAs and superconducting detectors. I will continue in evaluating new improved versions of the detector and make sure that it will suit IBM testing needs.
Optometrix, with a new, low cost PICA tool. From the very beginning, I have been using my years of experience in optical testing to collaborate with them as a consultant. I was able to aid their development process both by shortening their development time by several months, and by making sure that the tool will satisfy present and future IBM needs.

I have also continued my collaboration with research centers such as:

CNES (French Space Agency), France, on the development of new analysis technique for improving the signal to noise ration of PICA waveforms.
Politecnico di Milano, Italy, on the detector development area. Using their expertise in the electronic front-end design, we were able to demonstrate improved time resolution and reduced jitter in the measurements.

Through the past years I have also actively participated in discussions inside the testing and failure analysis communities. As an expert of time correlated single photon counting techniques as well as near-infrared single photon detectors, I have participated in round tables among different companies (such as IBM and Advanced Micro Devices, AMD) to discuss the present and future of the PICA technique and understand the limiting factors that need being addressed in order to maintain and extend its usability in future technology nodes.

Besides tools, detectors and measurement setups, I have specifically contributed to the advance of packaging and cooling capability for optical testing of integrated circuits. In particular, I have collaborated on the design of a custom cooling fixture using a diamond window film to remove heat from the chip under test while still being able to detect light emitted through the backside of the chip. Using this fixture, we were able to demonstrate more than 130W of heat removal capability in a paper presented at the International Test Conference this year. I also worked on the invention and development of a novel optical package using a thin layer of transparent material to hold a thinned chip in a dual in line package. This patent allows for both optical access to the chip through its back side and wire bonding from the front side.

I have authored and co-authored several patent applications related to the development of new optical testing tools:

One relates to the combination of PICA with other optical based techniques such as laser stimulation. The combination of these two methodologies in a single tool allows for both stimulating and probing a circuit in a completely non invasive and contactless way.
Another one allows for replacing the jitter electrical trigger that is needed to sync the chip and PICA tool with an optical signal picked up from the chip or injected with a laser.
Another application allows for creating an image in time of the emission by just using a single pixel detector.

Novel applications of optical techniques to circuit testing and diagnostics

During these years with IBM I have continued advancing the state of the art of optical testing techniques by always developing new areas of applications and testing methodologies. I have already mentioned the novel technique for studying carrier recombination and latchup ignition, as well as several techniques based on the measurement of the Light Emission from Off-State Leakage Current (LEOSLC).

By using the superconducting detector we were the first able to use the fainter emission from the p-type transistor to measure pulse duration and signal duty cycle. We applied this capability to three major application areas:

The measurement of the phase error of on-chip clock generators, such as Phase-Locked Loops (PLLs). At the time we demonstrated this technique, the phase error could not be measured by electrical means. Our results, published in international conferences, helped to solve several problems on IBM products, reducing their time to market. Moreover, we were able to bring the attention of the test community to this problem and stimulate the development of on-chip and off-chip electrical sensors for the phase error, previously not available.
The study of duty cycle degradation when a signal propagates along several gates in a critical path. This study allowed us to better understand the mechanism affecting the duty cycle distortion, improve the models of the devices available to the designers to foresee possible problems, as well as validate circuits designed to correct this problem. Once again, these methods have been applied on IBM chips and saved development money.
The estimation of CMOS gate switching time, by measuring the optical waveform of both n-type and p-type transistor and by using simulation of the optical emission based on the emission model previously developed. Switching time is a very important information for chip design, test, and diagnostic. In fact it allows for understanding if the gate is working properly or if the output load was correctly estimated during design, simulations, etc. Moreover, because of the stringent constrains that apply to future high-speed microprocessors built in 45 nm technology node, this type of timing information becomes more and more important for hardware-model correlation improvement. The final goal is the improvement of circuit reliability and process yield by studying process variation effects, marginality issues, AC defects, and burn-in degradation. From the theory of the hot-carrier photoemission it is known that when the input voltage of a CMOS gate switches from logic low to logic high (high to low) both the n- and p-type transistors emit a light pulse: two peaks for each transition. These two peaks take place at different moments in time; corresponding roughly to when the input signal crosses the thresholds of the transistors. This phenomenon can be briefly explained by the fact that the emission intensity depends exponentially on the electric field in the channel, which is at its maximum when the gate voltage reaches the threshold of each transistor. The innovative method we have developed and applied to real life measurements takes advantage of the separation of the peaks for estimating the signal switching time.