(2026)
31. H. Jeong, J. Lee, H. Lee, and S. Kang, "Subarray-Based Victim-Centric Per-Row Counting for Mitigating RowHammer"
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., To Be Published. [Early Access]
30. Y. Hwang, Y. Kang, and H. Lee, "DPR-PIM: Diagnosis and Pipelined Repair Architecture for Processing-in-Memory" - 대표논문
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 34, no. 5, pp. 1567-1580, May 2026. [IEEE Xplore]
29. S. Lee, J. Lee, H. Lee, and S. Kang, "VASE: Vector Memory using Bit-Level Address Segmentation for High-Speed Memory Testing"
IEEE Trans. Circuits Syst. I, vol. 73, no. 1, pp. 334-346, Jan. 2026. [IEEE Xplore]
(2025)
28. H. Yun, H. Lim, H. Lee, and S. Kang, "Multistage Enhanced Diagnosis with Fault Candidate Reduction"
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 44, no. 9, pp. 3648-3652, Sep. 2025. [IEEE Xplore]
27. S. H. Shin, M. Cheong, H, Lee, B. Kim, and S. Kang, "A Novel CNN-based Redundancy Analysis Using Parallel Solution Decision"
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 44, no. 7, pp. 2789-2802, Jul. 2025. [IEEE Xplore]
26. H. Lee, J. Lee, and S. Kang, "An Efficient Test Architecture Using Hybrid Built-In Self-Test for Processing-In-Memory" - 대표논문
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 33, no. 5, pp. 1452-1456, May 2025. [IEEE Xplore]
25. J. Yoon, H. Lee, Y. Moon, S. H. Shin, and S. Kang, "A Built-In Self-Repair With Maximum Fault Collection and Fast Analysis Method for HBM"
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 44, no. 5, pp. 2014-2025, May 2025. [IEEE Xplore]
24. H. Lee, J. Lee, and S. Kang, "A Robust Test Architecture for Low-Power AI Accelerators" - 대표논문
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 44, no. 4, pp. 1581-1594, Apr. 2025. [IEEE Xplore]
23. J. Lee, H. Lee, S. Lee, and S. Kang, "A Cost-Effective Per-Pin ALPG for High-Speed Memory Testing"
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 33, no. 3, pp. 867-871, Mar. 2025. [IEEE Xplore]
22. S.-H Shin, H. Lee, and S. Kang, "Effective Parallel Redundancy Analysis Using GPU for Memory Repair"
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 33, no. 2, pp. 462-474, Feb. 2025. [IEEE Xplore]
21. S. Lee, H. Lee, J. Lee, and S. Kang, "A New Pipelined Output Data Reducer of BOST for Improved Parallelism"
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 44, no. 2, pp. 765-776, Feb. 2025. [IEEE Xplore]
(2024)
20. Y. Yoo, H. Lee, S. H. Shin, and S. Kang, "RAPID: Redundancy Analysis with Parallelized and Intelligent Distribution"
IEEE Access, vol. 13, pp. 2089-2100, Dec. 2024. [IEEE Xplore]
19. H. Yun, H. Lim, H. Lee, D. Yoon, and S. Kang, "An Efficient Scan Diagnosis for Intermittent Faults using CNN with Multi-Channel Data"
IEEE Access, vol. 12, pp. 146463-146475, Oct. 2024. [IEEE Xplore]
18. H. Lee, J. Park, and S. Kang, "An Area-Efficient Systolic Array Redundancy Architecture for Reliable AI Accelerator" - 대표논문
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 32, no. 10, pp. 1950-1954, Oct. 2024. [IEEE Xplore]
17. S.-H. Shin, H. Lee, and S. Kang, "GRAP: Efficient GPU-based Redundancy Analysis Using Parallel Evaluation for Cross Faults"
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 43, no. 8, pp. 2518-2531, Aug. 2024. [IEEE Xplore]
16. J. Lee, H. Lee, S. Lee, and S. Kang, "A New ISA for High-Speed and Area-Efficient ALPG"
IEEE Trans. Circuits Syst. II, vol. 71, no. 7, pp. 3358-3362, Jul. 2024. [IEEE Xplore]
15. H. Lee, S. Lee, and S. Kang, "RA-Aware Fail Data Collection Architecture for Cost Reduction"
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 32, no. 6, pp. 1136-1149, Jun. 2024. [IEEE Xplore]
14. H. Lee, S. Lee, and S. Kang, "A New Fail Address Memory Architecture for Cost-Effective ATE"
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 43, no. 4, pp. 1260-1273, Apr. 2024. [IEEE Xplore]
(2023)
13. H. Lee, J. Kim, J. Park, and S. Kang, "STRAIT: Self-Test and Self-Recovery for AI Accelerator" - 대표논문
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 42, no. 9, pp. 3092-3104, Sep. 2023. [IEEE Xplore]
12. H. Lee, S. H. Shin, Y. Yoo, and S. Kang, "TRUST: Through-Silicon Via Repair Using Switch Matrix Topology" - 대표논문
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 42, no. 7, pp. 2377-2390, Jul. 2023. [IEEE Xplore]
(2022)
11. H. Kim, H. Lee, D. Han, and S. Kang, "MultiBank Optimized Redundancy Analysis Using Efficient Fault Collection"
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 41, no. 8, pp. 2739-2752, Aug. 2022. [IEEE Xplore]
10. H. Lee, Y. Yoo, S.-H Shin, and S. Kang, "ECMO: ECC Architecture Reusing Content Addressable Memories for Obtaining High Reliability in DRAM"
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 30, no. 6, pp. 781-793, Jun. 2022. [IEEE Xplore]
(2021)
9. D. Han, H. Lee, S. Lee, and S. Kang, "ECC-Aware Fast and Reliable Pattern Matching Redundancy Analysis for Highly Reliable Memory"
IEEE Access, vol. 9, pp. 133274-133288, Oct. 2021. [IEEE Xplore]
8. D. Han, H. Lee, and S. Kang, "Effective Spare Line Allocation Built-in Redundancy Analysis with Base Common Spare for Yield Improvement of 3D Memory"
IEEE Access, vol. 9, pp. 76716-76729, May 2021. [IEEE Xplore]
7. H. Lee, H. Oh, and S. Kang, "On-Chip Error Detection Reusing Built-in Self-Repair for Silicon Debug"
IEEE Access, vol. 9, pp. 56443-56456, Apr. 2021. [IEEE Xplore]
(2020)
6. J. Kim, H. Lee, S. Jang, and S. Kang, "Fine-Grained Defect Diagnosis for CMOL FPGA Circuits"
IEEE Access, vol. 8, pp. 163140-163151, Sep. 2020. [IEEE Xplore]
5. T. Kim, H. Lee, and S. Kang, "GPU-Based Redundancy Analysis Using Concurrent Evaluation"
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 28, no. 3, pp. 805-817, Mar. 2020. [IEEE Xplore]
(2019)
4. H. Lee, D. Han, S. Lee, and S. Kang, "Dynamic Built-In Redundancy Analysis for Memory Repair"
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 27, no. 10, pp. 2365-2374, Oct. 2019. [IEEE Xplore]
(2018)
3. H. Lee, K. Cho, D. Kim, and S. Kang, "Fault Group Pattern Matching with Efficient Early Termination for High-Speed Redundancy Analysis"
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 37, no. 7, pp. 1473-1482, Jul. 2018. [IEEE Xplore]
2. H. Lee, J. Kim, K. Cho, and S. Kang, "Fast Built-in Redundancy Analysis Based on Sequential Spare Line Allocation"
IEEE Trans. Rel., vol. 67, no. 1, pp. 264-273, Mar. 2018. [IEEE Xplore]
1. D. Kim, H. Lee, and S. Kang, "An Area-efficient BIRA with 1D Spare Segments"
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 26, no. 1, pp. 206-210, Jan. 2018. [IEEE Xplore]