RESEARCH

Processing-in-Memory (PiM)

Design for PiM

Bandwidth-Aware Operand Expansion
Decompression-Assisted Compute Architecture
Format-Aware Dataflow Optimization
Reliability-Aware Architecture
Fault-Resilient Data Organization

Test & Repair for PiM

Design-for-Testability
Built-In Self-Test for Compute Units
Online Test Architecture
Fault-Aware Repair Strategy
Fault-Tolerant Compute Recovery
Redundancy-Aware Repairability Design

AI Accelerator

Design & Test for AI Accelerator

Power-Aware AI Accelerator Design
Design-for-Testability
Built-In Self-Test & Diagnosis
Low-Power Test Strategy
Fault Modeling and Analysis
Test Pattern Generation and Compression

Repair for AI Accelerator

Repairability-Aware Architecture
Redundant PE Allocation Strategy
Built-In Self-Repair
Fault Mapping and Remapping
Runtime Fault Recovery
Reliability-Aware Resource Management

High-Bandwidth Memroy (HBM)

Memory Reliability & Security

Row Hammer Vulnerability Analysis
Disturbance-Aware Fault Modeling
Hardware Mitigation for Row Hammer Errors
Runtime Detection of Aggressor Rows
Row Hammer-Aware Memory Architecture
Memory Fault Prediction and Prevention

Memory Test & Repair

Memory Test Scheduling
Self-Test for Memory Arrays
Redundancy-Based Memory Repair
Test Data Compression
Peripheral Logic Fault Detection

TSV Test & Repair

Timing Analysis and Optimization
Fault Localization
Repair Path Planning
Redundancy-Aware Recovery
Reliability Monitoring

System-on-Chip (SoC)

Test & Diagnosis for SoC

Design-for-Testability
Built-In Self-Test & Diagnosis
Power-Aware Test Compression
Adaptive Test Scheduling
Scan Chain Insertion & Optimization

Security for SoC

Secure Scan Architecture
Dynamic Key-Based Scan Protection
Secure Test Access Control
Logic Locking for IP Protection
SAT-Resilient Obfuscation Design

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