(2025)
23. S. Park and H. Lee, "Priority-Based Fault Reordering for Reducing Memory Repair Time,"
in Proc. IEEE Int. SoC Design Conf., Busan, Korea, Oct. 2025, pp. 1-2. [IEEE Xplore]
22. J. Gwak and H. Lee, "Mini CAM-Based Redundancy Architecture for Reducing Area Overhead,"
in Proc. IEEE Int. SoC Design Conf., Busan, Korea, Oct. 2025, pp. 1-2. [IEEE Xplore]
21. Y. Kim and H. Lee, "An Online Testing Scheme for PIM Using Pipeline Register Pair Comparison,"
in Proc. IEEE Int. SoC Design Conf., Busan, Korea, Oct. 2025, pp. 1-2. [IEEE Xplore]
20. Y. Hwang and H. Lee, "A Design for Tolerating Multiple Faults in Processing-in-Memory,"
in Proc. IEEE Int. SoC Design Conf., Busan, Korea, Oct. 2025, pp. 1-2. [IEEE Xplore]
(2024)
19. S. Lee, H. Lee, J. Lee, and S. Kang, "APAPG: Address Pre-Processed ALPG for High-Speed Linear Test,"
in Proc. IEEE Int. SoC Design Conf., Hokkaido, Japan, Aug. 2024, pp. 396-397. [IEEE Xplore]
18. J. Lee, S. Lee, H. Lee, and S. Kang, "Scan Architecture with Data Observation for Multiple Scan Cell Fault Diagnosis,"
in Proc. IEEE Int. SoC Design Conf., Hokkaido, Japan, Aug. 2024, pp. 392-393. [IEEE Xplore]
(2023)
17. Y. Yoo, H. Lee, S.-H. Shin, and S. Kang, "GPU-Based Redundancy Analysis using Partitioning Method for Memory Repair,"
in Proc. IEEE Int. SoC Design Conf., Jeju Island, Korea, Oct. 2023, pp. 311-312. [IEEE Xplore]
16. H. Lee, Y. Yoo, S.-H. Shin, and S. Kang, "Redundancy Analysis Simplification Scheme for High-Speed Memory Repair,"
in Proc. IEEE Int. SoC Design Conf., Jeju Island, Korea, Oct. 2023, pp. 339-340. [IEEE Xplore]
(2022)
15. J. Kim, H. Lee, J. Park, and S. Kang, "ZOS: Zero Overhead Scan for Systolic Array-based AI accelerator,"
in Proc. IEEE Int. SoC Design Conf., Gangneung, Korea, Oct. 2022, pp. 360-361. [IEEE Xplore]
14. S.-H. Shin, H. Lee, S. Lee, Y. Yoo, and S. Kang, "An Improved Early Termination Methodology Using Convolutional Neural Network,"
in Proc. IEEE Int. SoC Design Conf., Gangneung, Korea, Oct. 2022, pp. 21-22. [IEEE Xplore]
13. S. Lee, H. Lee, Y. Yoo, S.-H. Shin, and S. Kang, "PROG: Per-Row Output Generator for BOST,"
in Proc. IEEE Int. SoC Design Conf., Gangneung, Korea, Oct. 2022, pp. 23-24. [IEEE Xplore]
12. H. Lee, S. Lee, Y. Yoo, S.-H Shin, and S. Kang, "FAME: Fault Address Memory Structure for Repair Time Reduction,"
in Proc. IEEE Int. SoC Design Conf., Gangneung, Korea, Oct. 2022, pp. 31-32. [IEEE Xplore]
(2021)
11. S.-H. Shin, H. Lee. Y. Yoo, and S. Kang, "An Effective Spare Allocation Methodology for 3D Memory Repair with BIRA,"
in Proc. IEEE Int. SoC Design Conf., Jeju Island, Korea, Oct. 2021, pp. 429-430. [IEEE Xplore]
10. Y. Yoo, H. Lee, S.-H Shin, and S. Kang, "Post-bond Repair of Line Faults with Double-bit ECC for 3D Memory,"
in Proc. IEEE Int. SoC Design Conf., Jeju Island, Korea, Oct. 2021, pp. 427-428. [IEEE Xplore]
(2020)
9. H. Lee, K. Cho, S. Kang, W. Kang, S. Lee, and W. Jeong, "Fail Memory Configuration Set for RA Estimation,"
in Proc. IEEE Int. Test Conf., Washington, DC, USA, Nov. 2020, pp. 1-9. [IEEE Xplore]
8. H. Lee, D. Han, H. Kim, and S. Kang, "Redundancy Analysis Optimization with Clustered Known Solutions for High Speed Repair,"
in Proc. IEEE Int. SoC Design Conf., Yeosu, Korea, Oct. 2020, pp. 51-52. [IEEE Xplore]
7. J. Kim, H. Lee, S. Jang, H. Kim, and S. Kang, "Memory-like Defect Diagnosis for CMOL FPGAs,"
in Proc. IEEE Int. SoC Design Conf., Yeosu, Korea, Oct. 2020, pp. 139-140. [IEEE Xplore]
6. H. Lee, D. Han, H. Kim, and S. Kang, "W-ERA: One-Time Memory Repair with Wafer-Level Early Repair Analysis for Cost Reduction,"
in Proc. IEEE Int. Test Conf. Asia, Taipei, Taiwan, Sep. 2020, pp. 94-99. [IEEE Xplore]
(2019)
5. H. Lee, D. Han, S. Lee, and S. Kang, "Redundancy Analysis based on Fault Distribution for memory with complex spares,"
in Proc. IEEE Int. SoC Design Conf., Jeju Island, Korea, Oct. 2019, pp. 235-236. [IEEE Xplore]
(2018)
4. D. Han, H. Lee, S. Lee, M. Moon, and S. Kang, "3D Memory Formed of Unrepairable Memory Dice and Spare Layer,"
in Proc. TENCON, Jeju Island, Korea, Oct. 2018, pp. 1362-1363. [IEEE Xplore]
(2017)
3. D. Han, H. Lee, D. Kim, and S. Kang, "A New Repair Scheme for TSV-based 3D Memory using Base Die Repair Cells,"
in Proc. IEEE Int. SoC Design Conf., Seoul, Korea, Nov. 2017, pp. 11-12. [IEEE Xplore]
(2016)
2. K. Cho, J. Kim, H. Lee, and S. Kang, "Discussion of Cost-effective Redundancy Architectures,"
in Proc. IEEE Int. SoC Design Conf., Jeju Island, Korea, Oct. 2016, pp. 97-98. [IEEE Xplore]
(2015)
1. H. Lee, J. Lee, H. Lim, and S. Kang, " A Scan Segment Skip Technique for Low Power Test,"
in Proc. IEEE Int. SoC Design Conf., Gyeongju, Korea, Nov. 2015, pp. 127-128. [IEEE Xplore]