High Speed SerDes Course

📘 What the Course Will Cover

Drawing on extensive research and tape-out experience, this course will demystify the complete Wireline transceiver architecture:

• The Channel & Physics of Loss: Understanding lumped vs. distributed transmission line models, skin effect, dielectric loss, and how PCB traces and packaging compound signal attenuation.

• Jitter & Noise: Breaking down Random Jitter (RJ) vs. Deterministic Jitter (DJ), phase noise, and building link timing budgets.

• Transmitter (TX) Design & FFE: Designing voltage-mode and current-mode logic (CML) drivers, and implementing Feed-Forward Equalization (FFE) to pre-emphasize fast transitions and de-emphasize long runs of identical bits.

• Receiver (RX) Equalization: Deep-dives into Continuous-Time Linear Equalizers (CTLE) with active inductors for high-frequency gain peaking, and Decision Feedback Equalizers (DFE) to cancel post-cursor ISI without amplifying noise.

• Clocking Systems: The critical role of LC-tank and Ring-Oscillator Phase-Locked Loops (PLLs), and Clock and Data Recovery (CDR) architectures utilizing phase detectors.

• Link Closure: Bringing it all together with full end-to-end budgets, bathtub curves, compliance testing, and lab bring-up flows.