High Speed PLLs

Publications List

1. [C1] A Low Power, High Conversion gain CMOS Inductorless Frequency Doubler for 1.25-20 GHz Frequency Synthesis in mm-wave Receivers, Javed S. Gaggatur and Pratik Deshmukh, 2018 IEEE MTT-S International Microwave and RF Conference (IMARC), Nov 28, 2018, Kolkata, India

2. [C2] A 1.25 - 20 GHz Wide Tuning Range Frequency Synthesis for 40 Gb/s SerDes Application, Javed S Gaggatur and Abhishek Chaturvedi, VLSI Design and Test Symposium (VDAT) 2019, July 4-6, 2019 Indore, India.

3. [J1] A 5 GHz Interger-N PLL with spur reduction sampler, Debbut Biswas, Javed S. Gaggatur and Sankar Reddy - Electronics Letters, 2019

4. [C3] On-chip Temperature Compensated 2.5 GHz to 10GHz Multi-band LC-VCO Phase Locked Loop for Wireline Applications, Javed S. Gaggatur, 2019 IEEE MTT-S International Microwave and RF Conference (IMARC), Dec 13, 2019, Mumbai, India

5. [C4] A 1.8–6.3 GHz Quadrature Ring VCO-based Fast-settling PLL for Wireline I/O in 55nm CMOS, Javed S. Gaggatur - 2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID), Feb 20-24, 2021, Guwahati, India