Advanced Analog IC Design

IEEE Conference Publication by the mentees

1. [C10] A High-PSRR, Ultra-Low Quiescent Current, Capless LDO Regulator Using a Self-Biased Recycling Folded-Cascode Error Amplifier in 90nm CMOS, A. Ilyas, A. Khan, N. Alam and G. S. Javed, "" 2025 IEEE DELCON - International Conference on Recent Smart Technologies in Engineering for Sustainable Development, New Delhi, India, 2025, 

2. [C9] Agile Frequency Synthesis for a sub-100µW Wake-up Receiver, Shaheeda FS Vajrala, GS Javed , 2025 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD)  

3. [C8] A 5GHz Gain-Bandwidth Op-Amp in 180nm CMOS Technology, M. Reza, A. Sharma, A. Malik, M. Hussain, N. Alam and G. S. Javed, 2024 IEEE 4th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)

4. [C7] A 0-24mA, 1.2V/1.8V Dual Mode Low Dropout Regulator Design for Efficient Power Management in Battery-Powered Systems, M. Reza, N. Alam and S. J. Gaggatur, 2024 28th International Symposium on VLSI Design and Test (VDAT)

5. [C2] A 0.6 V, 2nd order low-pass Gm-C filter using CMOS inverter-based tunable OTA with 1.114 GHz cut-off frequency in 90nm CMOS technology, Nisarga Ramesh and Javed S. Gaggatur, 2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID), 2021, pp. 305-309, doi: 10.1109/VLSID51830.2021.00057. 

6. [C1] An 860MHz-1960MHz Multi-band Multi-stage Rectifier for RF Energy Harvesting in 130nm CMOS,  Javed S. Gaggatur and Shaheeda F. S. Vajrala, 2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bangalore, India, 2020, pp. 1-4, doi: 10.1109/CONECCT50063.2020.9198677.