4-bit SAP Processor Design in Verilog (Quartus Implementation)
Minimal processor architecture for instruction sequencing and digital design
Project Overview
This project implemented a Simple-As-Possible (SAP) processor to design a 4-bit Program Counter (PC) using Verilog HDL in Intel Quartus. The SAP processor model showcases the fundamentals of instruction sequencing, data flow, and control logic, making it a powerful platform for demonstrating core processor design and verification skills.
Key Features
⚙️ 4-bit Program Counter: Instruction sequencing for basic computation
💻 Verilog RTL Implementation: Modular design of datapath and control logic
🛠️ Quartus Simulation & Debugging: Functional verification with FPGA development tools
Research Contributions
Designed and verified a 4-bit Program Counter and instruction execution pipeline
Modeled datapath elements (registers, ALU, control unit) in Verilog RTL
Conducted timing and waveform analysis using Quartus for reliable system behavior
Technical Achievements
Demonstrated a fully functional minimal processor architecture
Strengthened skills in RTL coding, digital simulation, and FPGA workflows
Applied best practices in modular hardware design and debugging
Applications
Educational tool for computer architecture and digital design concepts
Foundation for building more advanced custom processors and microcontrollers
Training ground for RTL verification and hardware prototyping
Impact and Recognition
This project highlights hands-on expertise in processor architecture, Verilog design, and FPGA-based simulation, serving as a stepping stone toward advanced research in VLSI and computer architecture.