• Feb. 2022

• Thesis

Agile and Accurate Compact Model Parameter Extraction Methodology Utilizing Adaptive Pattern Search and Deep Reinforcement Learning

• Feb. 2022

• Thesis

Multivariate Predictive Modeling and Process Optimization with Sensitivity Analysis based on Neural Network

• Feb. 2022

• Thesis

Pure-HfOx Ferroelectricity for Next-generation Memory Devices,

• Feb. 2022

• Thesis

Variation-Aware Transistor Design Guide for Various Operating Environments Using Sub- 7nm Advanced Logic Technology

• Feb. 2022

• Thesis

Hardware Implementation of Artificial Synaptic Devices Using Memristor Crossbar Array

• Feb. 2022

• Thesis

Accurate and Low-Latency Spiking Neural Networks with Capacitor-Based Synaptic Devices

• Feb. 2021

• Thesis

SiGe Nanosheel Tunnel Field-Effect Transistor with High Current Drivability

• Feb. 2021

• Thesis

Nano-wedge RRAM Cross-point Array with Nickel Silicide Bottom Electrode as a Synaptic Device for Neuromorphic Computing Applications

• Feb. 2020

• Thesis

Polysilicon-channel Synapse with Asymmetric Dual Gate for Hardware Neuromorphic Systems

• Aug. 2020

• Thesis

Low Power Synaptic Device using Positive Feedback Field Effect Transistor with Charge Trap Layer

• Feb. 2020

• Thesis

Nano-structured Resistive Random Access Memory for Neuromorphic System

• Feb. 2020

• Thesis

Surface Ge-rich SiGe Channel Tunnel Field-Effect Transistor Fabricated by Ge Condensation Technique

• Aug. 2018

• Thesis

Layer Selection by Multi-level Permutation in Three-Dimensional Stacked NAND Flash Memory

• Feb. 2019

• Thesis

Integrate-and-Fire Neuron Circuit with Positive Feedback Field Effect Transistor for Low Power Operation

• Feb. 2018

• Thesis

Highly compact and accurate circuit-level macro modeling of charge-trap flash memory

• Aug. 2018

• Thesis

Tunnel Field-Effect Transistor with Thick Drain-Side Oxide for Low Gate-Drain Capacitance

• Aug. 2017

• Thesis

SiNx-Based Resistive Memory with Built-in Selectors

• Aug. 2017

• Thesis

Methods for Threshold Voltage Setting of String Select Transistors in Channel Stacked NAND Flash Memory

• Feb. 2017

• Thesis

Compact Neuromorphic System with Four-Terminal Si-Based Synaptic Devices for Spiking Neural Networks

• Feb. 2017

• Thesis

Silicon-Based Synaptic Transistor for Neuromorphic Computing systems

• Aug. 2016

• Thesis

Vertical Tunnel Field-Effect Transistors with Tunnel-Direction Perpendicular to the Channel for Low Power Operation

• Feb.  2017

• Thesis

High-sensitive Low Power Tunneling Field Effect Transistor Biosensor for Multiplexed Sensing Application

• Feb. 2016

• Thesis

Nano-structured RRAM for Ultra High Density and Low Power Memory

• Feb. 2016

• Thesis

Channel-Stacked NAND Flash Memory with High-κ Charge Trapping Layer for High Scalability

• Aug. 2014

• Thesis

Analysis and Improvement of Internal Quantum Efficiency in GaN-based LEDs,

• Feb. 2015

• Thesis

Tunnel Field-Effect Transistor with Si/SiGe Materials for High Current Drivability,

• Feb. 2014

• Thesis

L-shaped Tunnel Field-Effect Transistors (L-shaped TFETs) with High Current Drivability and Low Subthreshold Swing

• Aug. 2014

• Thesis

3-Dimensional NAND Flash Memory having Tied Big-line and Ground Select Transitor (TiGer)

• Aug. 2013

• Thesis

Silicon Nanowire Tunneling Field-Effect Transistor Compatible to Complementary Metal-Oxide-Semiconductor Technology

• Feb. 2014

• Thesis

Fast and Reproducible pH Detection with Nanowire Field Effect Transistors,

• Feb. 2013

• Thesis

Gated-Twin-Bit (GTB) SONOS NAND flash memory for high density nonvolatile memory

• Aug. 2013

• Thesis

Channel Stacked NAND Flash Memory with Layer Selection by Multi-Level Operation,

• Aug. 2012

• Thesis

Study on gradual switching behavior in reset transition of TiO2-based resistive switching memory and its mechanism

• Aug. 2012

• Thesis

Three-dimensional NAND flash architecture based on Channel Stacked Array (CSTAR)

• Feb. 2012

• Thesis

Poly-Silicon Quantum Dot Single-Electron Transistors

• Aug. 2012

• Thesis

Oxide based RRAM: area effect on reset current reduction in unipolar RRAM by using scaled cell structure

• Aug. 2011

• Thesis

Characterization and Optimization of Charge Trapping Behaviors for Non-Volatile Memory (NVM) Device

• Aug. 2011

• Thesis

Fabrication of Arch Type SONOS Flash Memory Array

• Aug. 2011

• Thesis

Research of Cone-Type SONOS Flash Memory

• Aug. 2011

• Thesis

Program/Erase/Retention Modeling of Nitride-Based Charge Trapping Flash Memory and its Characterization

• Aug. 2011

• Thesis

Research of Cone-Type SONOS Flash Memory,

• Aug. 2011

• Thesis

Program/Erase/Retention Modeling of Nitride-Based Charge Trapping Flash Memory and its Characterization

• Aug. 2010

• Thesis

Three-Dimensional STacked-ARray (STAR) NAND Flash Memory with Single-Crystal Silicon Nanowire and Virtual Source/Drain,

• Feb. 2011

• Thesis

Room-Temperature Operation of Single-Electron Transistor Using Recessed Channel Structure

• Feb. 2010

• Thesis

Folded NAND-Type Charge Trap Flash Memory Device with Bandgap-Engineered Storage Node and Its Array: Fabrication and Reliable Operation

• Feb. 2010

• Thesis

Asymmetric MOSFETs Using Novel Fabrication Method,

• Aug. 2009

• Thesis

Vertical-AND (V-AND) Array for High Density, High Speed, and Reliable Flash Memories,

• Feb. 2010

• Thesis

Fin and Recess Channel MOSFET for High Speed and Low Power DRAM Cell,

• Feb. 2007

• Thesis

Bottom-contact pentacene OTFTs using organic gate insulator and their application to organic circuits,

• Aug. 2007

• Thesis

Capacitorless 1-Transistor Dynamic Random Access Memory (DRAM) Cell,

• Feb. 2006

• Thesis

A Study on the characterization methodology of silicon nitride using the charge decay model of SONOS flash memories

• Feb. 2007

• Thesis

Nanoscale tri-gate CMOSFET architecture on Silicon-On-ONO (SOONO) substrate,

• Feb. 2005

• Thesis

Multiple-valued logics based on SET/CMOS hybrid architecture

• Feb. 2006

• Thesis

Impact-ionization metal-oxide-semiconductor (I-MOS) devices using avalanche breakdown mechanism

• Aug. 2004

• Thesis

Silicon quantum tunneling device based on band-to-band tunneling mechanism 

• Feb. 2005

• Thesis

BAVI-cell : a high-speed nanoscale SONOS memory with band-to-band tunneling initiated avalanche injection Mechanism

• Feb. 2004

• Thesis

Nanoscale SONOS nonvolatile memory devices based on sidewall patterning technique

• Feb. 2004

• Thesis

Multi-bit FLASH memories with trapping storages (SONOS) and their applications

• Feb. 2004

• Thesis

Novel 50nm MOSFETs with side-gates for virtual source/drain extension

• Feb. 2004

• Thesis

Design and fabrication of 30nm self-aligned FinFET

• Feb. 2002

• Thesis

Silicon Single-Electron Transistors With Depletion Gates and Their Application to Single-Electron Logic Circuit

• Aug. 1998

• Thesis

Deep Submicron Buried Channel pMOSFET Design and Fabrication

• Feb. 2022

• Thesis

Integrate-and-Fire Neuron with Capacitive Trans-Impedance Amplifier for Improving Linearity in Spiking Neural Networks

• Feb. 2020

• Thesis

Investigation of Novel Stacked Floating Fin Structured Gate-All-Around MOSFETs

• Aug. 2020

• Thesis

Resistive Switching Synaptic Device with High Rectification Ratio and its Impact on Spiking Neural Network

• Feb. 2019

• Thesis

Recognition and Speed Estimation of Moving Objects using Spiking Neural Network Incorporating Adaptive Neuron Circuit

• Feb. 2020

• Thesis

Simulation of the Effect of Parasitic Channel Height on Characteristics of Stacked Gate-All-Around Nanosheet FET

• Aug. 2017

• Thesis

Capacitance–voltage characterization of tunnel field effect transistors with a Si/SiGe heterojunction

• Feb. 2018

• Thesis

SPICE Simulation of the Neuromorphic System Composed of Neuron Circuit and Synaptic Device

• Feb. 2017

• Thesis

Analysis of Trapped Charge Migration at 3D NAND Flash Memory with Multi Level Operation

• Feb. 2017

• Thesis

Fabrication of Nano-Wedge Structured Resistive Switching Memory and Analysis on Its Switching Characteristics

• Aug. 2014

• Thesis

Neuron Circuit Using a Thyristor and Inter-Neuron Connection with Synaptic Device

• Feb. 2017

• Thesis

High Current Operation and Analysis on InGaN/GaN-based LED with Improved Hole Injection Structure

• Feb. 2013

• Thesis

Investigation of three dimensional NAND flash memory based on Gated STacked ARray (GSTAR)

• Feb. 2013

• Thesis

Investigation of biploar resistive switching characteristics of Si3N4-based RRAM with MIS structure

• Aug. 2012

• Thesis

Channel stacked array NAND flash memory with vertically stacked String Selection Line(SSL)

• Aug. 2012

• Thesis

Silicon-based floating-body synaptic transistor

• Aug. 2011

• Thesis

Investigation on the Characteristics of Stress-induced hump in Amorphous HfInZnO Thin Film Transistors

• Feb. 2012

• Thesis

Investigation of Vertical Type Single-Electron Transistor with Sidewall Spacer Quantum Dot

• Feb. 2011

• Thesis

Investigation of Bias Stress Instability in HfInZnO Thin Film Transistor

• Feb. 2011

• Thesis

Fabrication and Characteristics of Tunneling Field-Effect Transistor using Schottky Barrier Tunneling

• Feb. 2010

• Thesis

Arch NAND Flash Memory Array with Improved Virtual Source/Drain Performance

• Feb. 2011

• Thesis

Light and Temperature Effects on Negative Bias-Induced Instability of HfInZnO Amorphous Oxide Thin Film Transistor

• Feb. 2009

• Thesis

Fabrication and Characteristics of Self-Aligned Dual-Gate Single-Electron Transistors

• Feb. 2009

• Thesis

Fabrication and Characteristics of Folded Split Gate SONOS memory

• Feb. 2009

• Thesis

Fabrication Process of Vertical Field-induced Interband Tunneling Effect Transistor

• Feb. 2009

• Thesis

Fabrication and Analysis of the Gate-All-Around (GAA) Structure Silicon Nanowire MOSFET

• Feb. 2008

• Thesis

Investigation of Resistive Probe Used for Writing/Reading in Ferroelectric Material

• Aug. 2008

• Thesis

A Capacitor-less 1T-DRAM Cell Based on a Surrounding Gate Vertical Channel MOSFET with GIDL Write Operation

• Aug. 2007

• Thesis

Cone-Type SONOS Flash Memory Device with Improved Program/Erase Characteristics Using Field Concentration Effect

• Aug. 2007

• Thesis

Modeling of Program/Erase Characteristics of NAND-type SONOS Flash Memory

• Feb. 2007

• Thesis

Trench Tunneling Barrier Single-Electron Transistors (TSETs) Using Bandgap Increase by Quantum Confinement Effect

• Aug. 2007

• Thesis

New Capcitor-less 1T-DRAM Cell Based on a Double Gate MOSFET with Vertical Channel (DGVC Cell)

• Feb. 2006

• Thesis

Fabrication and SPICE Model Development of Field-induced Inter-band Tunneling Effect Transistors(FITETs)

• Feb. 2006

• Thesis

A Study on Double-Gate SOI FinFETs Using Sidewall Multi-Line Patterning Technique

• Feb. 2005

• Thesis

Silicon Quantum Tunneling Devices Based on Band-to-Band Tunneling Mechnism

• Aug. 2005

• Thesis

A Study on Electrical Performance Improvement of Bottom-Contact Type Organic Thin-Film Transistors Using Thin PMMA Surface Treatment Method

• Feb. 2004

• Thesis

Characterization of SONOS Memory Using Dual Carrier Separation Technique

• Aug. 2004

• Thesis

Fabrication and Characterization Single-Electron Transistors Using Anisotropic TMAH Wet Etch

• Feb. 2003

• Thesis

A study on fabrication of single electron transistors using nano-patterning technology

• Feb. 2004

• Thesis

Single-Electron Transistors and CMOS Devices Simulaneously Fabricate on SOI Wafer

• Feb. 2002

• Thesis

Development of Ultra-fine Process Technologies and Their Application to 30nm nMOSFETs

• Feb. 2003

• Thesis

Fabrication of Nanoscale SONOS Memories on an SOI Wafer and Their Low Voltage Operation

• Feb. 2002

• Thesis

Realization of Ultra-fine Multiple Lines Using Sidewall Structure

• Feb. 2002

• Thesis

Active Matrix Polymer Electroluminescent Display Driving Circuit Using CMOS Logic

• Feb. 2001

• Thesis

Fabrication of Molded-Gate MOSFET with Etch-back Process

• Feb. 2001

• Thesis

A Study on Single Electron Transistors with Electrically Induced Tunnel Barriers

• Feb. 2001

• Thesis

Suppression of Junction Leakage Current in CoSi2 with Preamorphization implantation

• Feb. 2001

• Thesis

A Study on Developing an Equipment for Measuring the Thickness of Ultra Thin Film Using the Principle of AFM

• Feb. 2000

• Thesis

A Study on Soft Breakdowns in Ultra-Thin Oxide of MOS Structures

• Feb. 2000

• Thesis

0.1um NMOSFET with Ultra-Shallow Junction Using As2+ 5keV Ion Implantation

• Feb. 1999

• Thesis

Fabrication and Characterization of a Single Electron Memory Cell

• Feb. 1999

• Thesis

Realization of Ultra-Fine Lines using Sidewall Structures and Their Application to nMOSFETs

• Feb. 1998

• Thesis

A Study on Single Electron Transistor with Dual Gate Structure

• Feb. 1998

• Thesis

Electrical Characterization of the Ultra Thin Gate Oxide Grown by Wet Oxidation and Its Application to CMOSFETs

• Feb. 1997

• Thesis

A Study on the Fabrication of Surface Channel 0.1um pMOSFETs

• Feb. 1997

• Thesis

 Study on the Fabrication of Surface Channel 0.1um CMOSFETs

• Feb. 1996

• Thesis

A Study on 0.1um nMOSFETs with Indium Implanted Channel,

• Feb. 1996

• Thesis

A Study on the Fabrication of 0.1um nMOSFETs using Retrograde Boron Channel LDD Structure