International
[154] Yoon Tae Jeong, Jin Ho Chang, Jae Seung Woo, and Woo Young Choi, "Hot Carrier Injection Analysis of High-Current Driving p-MOSFETs", International Conference on Electronics, Information, and Communication (ICEIC), Taipei, Taiwan, pp. 1302-1304, Jan. 28-31, 2024.
[153] Se Hyun Uhm, Jin Ho Chang, and Woo Young Choi, "Vertical NAND Flash Memory for Interference Suppression", International Conference on Electronics, Information, and Communication (ICEIC), Taipei, Taiwan, pp. 1299-1301, Jan. 28-31, 2024.
[152] Seon Ho Lee, Chang Heon Park, Hyung Jun Noh, and Woo Young Choi, "Nonvolatile Memory Based on Tunnel Field-Effect Transistors", International Conference on Electronics, Information, and Communication (ICEIC), Taipei, Taiwan, pp. 1305-1307, Jan. 28-31, 2024.
[151] Seung Hyeon Han and Woo Young Choi, "Variability Analysis of Ferroelectric Tunnel Field-Effect Transistors", International Conference on Electronics, Information, and Communication (ICEIC), Taipei, Taiwan, pp. 1215-1217, Jan. 28-31, 2024.
[150] Minjeong Ryu and Woo Young Choi, "Ferroelectric Tunnel Field-Effect Transistors for Reconfigurable Dynamic Logic-in-Memory Computing", International Conference on Electronics, Information, and Communication (ICEIC), Taipei, Taiwan, pp. 1092-1094, Jan. 28-31, 2024.
[149] Jin Wook Lee and Woo Young Choi, "Release Voltage Analysis of Nanoelectromechanical Memory Switches", International Conference on Electronics, Information, and Communication (ICEIC), Taipei, Taiwan, pp. 1089-1091, Jan. 28-31, 2024.
[148] Jae Seung Woo and Woo Young Choi, "Tunnel FET-based Charge Trapping Memory for Low Power Neuromorphic Systems", International Conference on Electronics, Information, and Communication (ICEIC), Taipei, Taiwan, pp. 1158-1161, Jan. 28-31, 2024.
[147] Jaemin Yeom, Minjeong Ryu, and Woo Young Choi, "Silicon-Germanium (SiGe) Metal-Ferroelectric-Metal-InsulatorSemiconductor (MFMIS) Tunnel Field-Effect Transistors (FeTFETs)", International Conference on Electronics, Information, and Communication (ICEIC), Taipei, Taiwan, pp. 1192-1194, Jan. 28-31, 2024.
[146] Jin Ho Chang, Jae Seung Woo, Suk Kang Sung, Ki Whan Song, and Woo Young Choi, "Dual-Channel Vertical NAND Flash Memory for the High-Density and High-Accuracy Ternary-State Quantized Neural Networks", International Conference on Electronics, Information, and Communication (ICEIC), Taipei, Taiwan, pp. 1056-1059, Jan. 28-31, 2024.
[145] Hyung Jun Noh, Chang Heon Park, Seon Ho Lee, and Woo Young Choi, "TFET-Based Nonvolatile Memory Optimization Regarding Trap Positions", International Conference on Electronics, Information, and Communication (ICEIC), Taipei, Taiwan, pp. 1204-1206, Jan. 28-31, 2024.
[144] Geun Tae Park and Woo Young Choi, "Binary Neural Networks Using Nanoelectromechanical Memory Switches", International Conference on Electronics, Information, and Communication (ICEIC), Taipei, Taiwan, pp. 1195-1197, Jan. 28-31, 2024.
[143] Chang Heon Park, Hyung Jun Noh, Seon Ho Lee, and Woo Young Choi, "Design Optimization of TFET-Based Memory", International Conference on Electronics, Information, and Communication (ICEIC), Taipei, Taiwan, pp. 1198-1200, Jan. 28-31, 2024.
[142] Changha Kim, Dong-Oh Kim, and Woo Young Choi, "Influence of Doping Concentrations of Gate-Source/Drain Overlap Region on MFMIS FeFETs", International Conference on Electronics, Information, and Communication (ICEIC), Taipei, Taiwan, pp. 1210-1212, Jan. 28-31, 2024.
[141] Bosung Jeon and Woo Young Choi, "Variation Mitigation in Analog Neuron Circuits Using SFS-PV Methods for Hardware Spiking Neural Networks", International Conference on Electronics, Information, and Communication (ICEIC), Taipei, Taiwan, pp. 1098-1100, Jan. 28-31, 2024.
[140] Junsu Yu, Donghyun Ryu, and Woo Young Choi, "Impact of Verification Errors on Off-Line Training in AND-Type Flash", International Conference on Electronics, Information, and Communication (ICEIC), Taipei, Taiwan, pp. 1060-1062, Jan. 28-31, 2024.
[139] Jonghyuk Park and Woo Young Choi, "Analog Neuron Circuits for Hardware-Based Spiking Neural Networks", International Conference on Electronics, Information, and Communication (ICEIC), Taipei, Taiwan, pp. 1201-1203, Jan. 28-31, 2024.
[138] Yeonwoo Kim and Woo Young Choi, "Current Mirroring Methods of AND-Type Synaptic Arrays", International Conference on Electronics, Information, and Communication (ICEIC), Taipei, Taiwan, pp. 1104-1106, Jan. 28-31, 2024.
[137] Gyuweon Jung, Jaehyeon Kim, Yujeong Jeong, Jinwoo Park, Wonjun Shin, Woo Young Choi, and Jong-Ho Lee, "New Gas Identification Method Using Gas Sensor-Amplifier Merged Array and In-Memory Computing-Based Preprocessing", International Electron Devices Meeting, San Francisco, U.S.A., pp. 33.5, Dec, 9-13, 2023.
[136] Jangsaeng Kim, Jiseong Im, Jonghyun Ko, Soochang Lee, Dongseok Kwon, Wonjun Shin, Joon Hwang, Ryun-Han Koo, Woo Young Choi, and Jong-Ho Lee, "First Demonstration of Innovative 3D AND-Type Fully-Parallel Convolution Block with Ultra-High Area-and Energy-Efficiency", International Electron Devices Meeting, San Francisco, U.S.A., pp. 23.4, Dec. 9-13, 2023.
[135] Dong-Oh Kim, Changha Kim, Yeonwoo Kim, and Woo Young Choi, "Improvement of Memory Operation through Junctionless Ferroelectric-Metal Field-Effect Transistors," International Microprocesses and Nanotechnology Conference (MNC), 17P-1-22, Nov. 2023.
[134] Geun Tae Park, Jin Wook Lee, Ji Soo Yoon, and Woo Young Choi, "Multi-Layer Nanoelectromechanical (NEM) Memory Switches for Efficient Multi-Path Routing," International SoC Design Conference (ISOCC), Jeju, Korea, pp. 75, Oct. 25-28, 2023.
[133] Jiseong Im, Donghee Kim, Woo Young Choi, and Jong-Ho Lee, "Hardware Implementation of Temporal Encoded Spiking Neural Networks and Its Application to Rapid Gas Detection," International Conference on Solid State Devices and Materials (SSDM), Nagoya, Japan, pp. 493-494, Sep. 5-8, 2023.
[132] Gyuweon Jung, Kangwook Choi, Wonjun Shin, Jinwoo Park, Donghee Kim, Jaehyeon Kim, Hunhee Shin, Chayoung Lee, Woo Young Choi, and Jong-Ho Lee, "High-sensitivity, low-power FET-type NO2 gas sensor using electron concentration control of gas-sensing material," International Conference on Solid State Devices and Materials (SSDM), Nagoya, Japan, pp. 183-184, Sep. 5-8, 2023.
[131] Arati Kumari Shah, Seongjae Cho, Woo Young Choi, and Hyungcheol Shin, "A Capacitor-Truncated Compact Neuron Circuit with Spike Frequency Tunability," Asia-Pacific Workshop on Advanced Semiconductor Devices, Yokohama, Japan, pp. 170-171, Jul. 10-11, 2023.
[130] Seung Hyun Ahn, Gyeong Wook Kwak, Siyoun Lee, Seong-Yeon Kim, Haesoon Oh, Jaesung Sim, and Woo Young Choi, "Influence of Channel Width Effect on Snapback Breakdown of MOSFETs," Asia-Pacific Workshop on Advanced Semiconductor Devices, Yokohama, Japan, pp. 104-105, Jul. 10-11, 2023.
[129] Gyeong Wook Kwak, Seung Hyun Ahn, Jin Ho Chang, and Woo Young Choi, "Influence of Trapped Electrons in Charge Trap Layers on Oxide Degradation of NAND Flash Memory," Asia-Pacific Workshop on Advanced Semiconductor Devices, Yokohama, Japan, pp. 102-103, Jul. 10-11, 2023.
[128] Minjeong Ryu and Woo Young Choi, "Investigation on the Ambipolar Behavior of Si1-xGex Tunnel Field-Effect Transistors," Asia-Pacific Workshop on Advanced Semiconductor Devices, Yokohama, Japan, pp. 90-91, Jul. 10-11, 2023.
[127] Jin Wook Lee, Jae Seong Lee, and Woo Young Choi, "Nanoelectromechanical Content-Addressable Memory as Nearest Neighbor Classifier," Asia-Pacific Workshop on Advanced Semiconductor Devices, Yokohama, Japan, pp. 112-113, Jul. 10-11, 2023.
[126] Geuntae Park, Jaeseong Lee, and Woo Young Choi, "Content-Addressable Memory Based on Nanoelectromechanical Memory Switches," Asia-Pacific Workshop on Advanced Semiconductor Devices, Yokohama, Japan, pp. 110-111, Jul. 10-11, 2023.
[125] Chang Heon Park and Woo Young Choi, "Non-volatile Memory Based on Tunneling Field-Effect Transistors Using Localized Charge Trap Layers," Asia-Pacific Workshop on Advanced Semiconductor Devices, Yokohama, Japan, pp. 108-109, Jul. 10-11, 2023.
[124] Jin Ho Chang and Woo Young Choi, "Recessed Channel Hemi-Cylindrical Vertical NAND Flash Memory for the Improvement of the Program/Erase Efficiency and Memory Density," Asia-Pacific Workshop on Advanced Semiconductor Devices, Yokohama, Japan, pp. 58-59, Jul. 10-11, 2023.
[123] Jae Seung Woo and Woo Young Choi, "Effective Hot Carrier Injection Programming for TFET-Based Flash Memory," Asia-Pacific Workshop on Advanced Semiconductor Devices, Yokohama, Japan, pp. 63-64, Jul. 10-11, 2023.
[122] Bosung Jeon, Taejin Jang, Seongjae Cho, Hyungcheol Shin, and Woo Young Choi, "Synapse Array with Buried Bottom Gate Structure for Neuromorphic Systems," IEEE Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, p. 3-03, Jun. 11-12, 2023.
[121] Junsu Yu, Donghyun Ryu, Taejin Jang, and Woo Young Choi, "Influence of Weight Transfer Error on Vector-Matrix Multiplication Using AND Array Architectures," IEEE Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, p. P-04, Jun. 11-12, 2023.
[120] [Invited] Woo Young Choi, "Monolithic 3D (M3D) Complementary Metal-Oxide-Semiconductor (CMOS)-Nano-Electromechanical (NEM) Hybrid Circuits for Low-Power and High-Speed Reconfigurable Logic (RL) Applications," IEEE International Conference on Nano/Micro Engineered and Molecular Systems (IEEE NEMS), Jeju, Republic of Korea, p. 183, May 14th-17th, 2023.
[119] Gyuweon Jung, Jaehyeon Kim, Wonjun Shin, Seongbin Hong, Yujeong Jeong, Chayoung Lee, Woo Young Choi, and Jong-Ho Lee, "Innovative Gas Sensing Method Using Transient Behavior of FET-Type Sensors with Gate Pulse Input," International Electron Devices Meeting, San Francisco, U.S.A., pp. 31.2, Dec. 3~7, 2022.
[118] Kyungho Hong, Sungjoon Kim, Tae-Hyeon Kim, Hyungjin Kim, and Woo Young Choi, "Extremely-Low-Power RRAM Array with Triple Tunneling Layers," International Microprocesses and Nanotechnology Conference (MNC), Tokushima, Japan, p.10B-2-3, Nov. 8th-11th, 2022.
[117] Dong-Oh Kim, Kitae Lee, Changha Kim, Sihyun Kim, Hyun-Min Kim, Daewoong Kwon, and Woo Young Choi, "Circular Ferroelectric Tunnel Junction for Endurance Improvement," International Microprocesses and Nanotechnology Conference (MNC), Tokushima, Japan, p.10P-3-12, Nov. 8th-11th, 2022.
[116] Jangsaeng Kim, Woo Young Choi, Byung-Gook Park, and Jong-Ho Lee, "Implementation of Homeostasis Functionality in Hardware-Based Spiking Neural Networks Using an STDP Learning Rule," International Conference on Solid State Devices and Materials (SSDM), Chiba, Japan, p.F-6-04, Sep. 26-29, 2022.
[115] Hyeongsu Kim, Inseok Lee, Woo Young Choi, Byung-Gook Park, and Jong-Ho Lee, "Variation-robust Binary Matrix-vector Multiplication Method," International Conference on Solid State Devices and Materials (SSDM), Chiba, Japan, p.F-6-03, Sep. 26-29, 2022.
[114] Seongbin Oh, Seungwhan Kim, Ho-Nam Yoo, Woo Young Choi, and Jong-Ho Lee, "Synaptic Devices Based on 3D-Semicircular NAND Flash Memory," International Conference on Solid State Devices and Materials (SSDM), Chiba, Japan, p.F-6-02, Sep. 26-29, 2022.
[113] Yujeong Jeong, Seongbin Hong, Gyuweon Jung, Wonjun Shin, Woo Young Choi, and Jong-Ho Lee, "H2S Sensing Characteristics of the Amplifier Circuit Consisting of pFET-type and Resistor-type Gas Sensors," International Conference on Solid State Devices and Materials (SSDM), Chiba, Japan, p.D-3-05, Sep. 26-29, 2022.
[112] Jiseong Im, Donghee Kim, Woo Young Choi, and Jong-Ho Lee, "A Neuromorphic Olfactory System Using Temporal Encoded Spiking Neural Networks," International Conference on Solid State Devices and Materials (SSDM), Chiba, Japan, p.D-3-03, Sep. 26-29, 2022.
[111] Gyuweon Jung, Wonjun Shin, Hunhee Shin, Seongbin Hong, Yujeong Jeong, Kangwook Choi, Jinwoo Park, Donghee Kim, Chayoung Lee, Jaehyeon Kim, Woo Young Choi, and Jong-Ho Lee, "Comparison of the H2S gas response characteristics of semiconductor gas sensors (HFGFET-, TFT-, and resistor-type) fabricated on the same wafer," International Conference on Solid State Devices and Materials (SSDM), Chiba, Japan, p.D-1-01, Sep. 26-29, 2022.
[110] Hyug Su Kwon, Jisoo Yoon, and Woo Young Choi, "Monolithic Three-Dimensional (M3D) Integration of Nanoelectromechanical (NEM) Memory Switches," Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Virtual, pp. 111-112, Jul. 7-8, 2022.
[109] Jang Woo Lee and Woo Young Choi, "π-shaped Tunnel FETs for Performance Enhancement," Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Virtual, pp. 49-50, Jul. 7-8, 2022.
[108] Bu-Il Nam, Youngha Choi, Sungki Hong, Ki-Young Dong, Wontaeck Jung, Sang-Won Park, Soon-Yong Lee, Dooyeun Jung, Byoung-Hee Kim, Eunkyoung Kim, Ki-Whan Song, Jai Hyuk Song, and Woo Young Choi, "Novel Electrical Detection Method for Random Defects on Peripheral Circuits in NAND Flash Memory," IEEE International Reliability Physics Symposium (IRPS), Dallas, TX, USA, pp. P40-1-P40-4, Mar. 27~31, 2022. doi: 10.1109/IRPS48227.2022.9764437
[107] Juwon Lee, Junho Seo, Jeonghun Nam, YongLae Kim, Ki-Whan Song, Jai Hyuk Song, and Woo Young Choi, "Electric Field Impact on Lateral Charge Diffusivity in Charge Trapping 3D NAND Flash Memory," IEEE International Reliability Physics Symposium (IRPS), Dallas, TX, USA, pp. P29-1-P29-5, Mar. 27~31, 2022. doi: 10.1109/IRPS48227.2022.9764447
[106] Dooyeun Jung, Youngha Choi, Jae In Lee, Bu-il Nam, Ki-Young Dong, Bohchang Kim, Eunkyoung Kim, Ki-Whan Song, Jai Hyuk Song, Myungsuk Kim, and Woo Young Choi, "Electrical Screening Method of V-NAND Flash Channel Hole Bending Defects." Proceedings from the 47th International Symposium for Testing and Failure Analysis (ISTFA). Phoenix, AZ, USA, pp. 306-308, Oct. 31–Nov. 4, 2021. doi.org/10.31399/asm.cp.istfa2021p0306
[105] Jeongin Choe, Taehyeon Kim, Saetbyeol Yoon, Sangyong Yoon, Ki-Whan Song, Jai Hyuk Song, Myungsuk Kim, and Woo Young Choi, "Wafer Pattern Recognition for Detecting Process Abnormalities in NAND Flash Memory Manufacturing." Proceedings from the 47th International Symposium for Testing and Failure Analysis (ISTFA). Phoenix, AZ, USA, pp. 406-409, Oct. 31–Nov. 4, 2021. doi.org/10.31399/asm.cp.istfa2021p0406
[104] Jisuk Kim, Earl Kim, Daehyeon Lee, Taeheon Lee, Daesik Ham, Miju Yang, Wanha Hwang, Jaeyoung Kim, Sangyong Yoon, Youngwook Jeong, Eunkyoung Kim, Ki-Whan Song, Jai Hyuk Song, Myungsuk Kim, and Woo Young Choi, "Machine Learning Based Optimization Technique for High-Capacity V-NAND Flash Memory." Proceedings from the 47th International Symposium for Testing and Failure Analysis (ISTFA). Phoenix, AZ, USA, pp. 20-22, Oct. 31–Nov. 4, 2021. doi.org/10.31399/asm.cp.istfa2021p0020
[103] Jae Seong Lee and Woo Young Choi, "Nonvolatile Content-Addressable Memory using Nanoelectromechanical Memory Switches for Data-Intensive Computation", Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Virtual(Japan), pp. 29-30, Aug. 26-27, 2021.
[102] Jae Seung Woo, Jang Woo Lee and Woo Young Choi, "Local Electric Field Concentration of Tunnel Field-Effect Transistors", Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Virtual(Japan), pp. 69-70, Aug. 26-27, 2021.
[101] Hyug Su Kwon and Woo Young Choi, "Island-Style Monolithic Three-Dimensional CMOS–Nanoelectromechanical Reconfigurable Logic Circuits," International Conference on Electronic Materials and Nanotechnology for Green Environment (ENGE), Jeju, Korea, pp. 31, Nov. 1-4, 2020.
[100] [Invited] Woo Young Choi, “Extremely-Low-Power Electron Devices: TFETs and NEM Devices," International Conference on Electronic Materials and Nanotechnology for Green Environment (ENGE), Jeju, Korea, pp. 43, Nov. 1-4, 2020.
[99] Jang Woo Lee and Woo Young Choi, "A Novel Gate-Normal Hetero-Gate-Dielectric (GHG) Tunnel Field-Effect Transistors (TFETs) for Improving Subthreshold Swing (SS)," International Conference on Electronic Materials and Nanotechnology for Green Environment (ENGE), Jeju, Korea, pp. 31, Nov. 1-4, 2020.
[98] Hyug Su Kwon and Woo Young Choi, "Slingshot Pull-in Mechanism of Nanoelectromechanical Memory Switches for Low Power Operation," Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Busan, Korea, pp. 209-210, Jul. 1-3, 2019.
[97] Jang Woo Lee and Woo Young Choi, "A Novel π-Shaped Tunnel Field-Effect Transistor (TFET) : Improving Subthreshold Swing (SS) with Extremely Suppressing Gate-Diagonal Tunneling," Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Busan, Korea, pp. 211-212, Jul. 1-3, 2019.
[96] Jae Seung Woo and Woo Young Choi, "Double-Gate PNPN TFET Using SiGe Channel for 1T DRAM Application", Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Busan, Korea, pp. 284-285, Jul. 1-3, 2019.
[95] Sung-Kun Park, Young-Jun Kwon, Tae-Ho Lee, Woo Young Choi, Gyuhan Yoon, Jun-Ho Lee, Seung-Duk Kim, Young-Dong Joo, Bok-Nam Song, and In-Wook Cho, "2T-SONOS Cell Using Novel Process Integration on HV-CMOS Platform for Versatile Application," International Memory Workshop (IMW), Monterey, CA, USA, pp. 16-19, May 12-15, 2019.
[94] Hyun Chan Jo and Woo Young Choi, "Novel Packaging Method of CMOS-Nano-Electromechanical (NEM) Hybrid Circuits", Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Kitakyushu, Japan, pp. 354-355, Jul. 2-4, 2018.
[93] Seongun Shin, Gyuhan Yoon, Seon Young Cha, Seon Soon Kim, Kwang Ho Ahn, Younghoon Cho, Woo Young Chung, Se Hyun Kim, and Woo Young Choi, "Reliability Modeling of DRAM Storage Capacitors", Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Kitakyushu, Japan, pp. 54-55, Jul. 2-4, 2018.
[92] [Invited] Woo Young Choi, “Monolithic 3D (M3D) Complementary Metal-Oxide-Semiconductor (CMOS)-Nanoelectromechanical (NEM) Hybrid Circuits," Electron Devices Technology and Manufacturing conference (EDTM), Kobe, Japan, pp. 125-127, Mar. 13-16, 2018.
[91] Jang Woo Lee, Hyug Su Kwon, and Woo Young Choi, “Tunnel FET-Nanoelectromechanical Hybrid Reconfigurable Logic Circuits," International SoC Design Conference (ISOCC), Seoul, Korea, pp. 67, Nov. 5-8, 2017.
[90] Woo Young Choi and Jang Woo Lee, “Improved Hetero-Gate-Dielectric Tunnel Field-Effect Transistors," International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, pp. 755-756, Sep. 19-22, 2017.
[89] In Eui Lim, Heesauk Jhon, Gyuhan Yoon, Jang Woo Lee, and Woo Young Choi, “Bias-Dependent On-Current Modeling of Short-Channel PMOSFETs with Hot-Carrier Stress Effects," Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Gyeongju, Korea, pp. 258-261, July. 3-5, 2017.
[88] [Invited] Woo Young Choi, “Monolithic 3D (M3D) Reconfigurable Logic Applications Using Extremely-Low-Power Electron Devices," China Semiconductor Technology International Conference (CSTIC), Shanghai, China, pp. I-7, Mar. 12-13, 2017.
[87] Woo Young Choi, “Monolithic 3D (M3D) Complementary Metal-Oxide-Semiconductor (CMOS)-Nano-Electromechanical (NEM) Hybrid Circuits for Low-Power and High-Speed Reconfigurable Logic (RL) Applications," The 5th Korea-EU Workshop on Nanotechnology, Seoul, Korea, pp. 24-25, Oct. 6, 2016.
[86] [Invited] Woo Young Choi, “Monolithic 3D (M3D) Complementary Metal-Oxide-Semiconductor (CMOS)-Nano-Electromechanical (NEM) Hybrid Circuits for Low-Power and High-Speed Reconfigurable Logic (RL) Applications," International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, pp. 7-8, Sep. 26-29, 2016.
[85] Woo Young Choi, Song Hun Choi, Jang Woo Lee, and In Huh, “Drain-Bias Dependency on Statistical Variability for Tunnel Field-Effect Transistors," International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, pp. 53-54, Sep. 26-29, 2016.
[84] Woo Young Choi, Song Hun Choi, Jang Woo Lee, and In Huh, “Influence of Line-Edge Roughness (LER) on Multiple-Gate (MG) Tunnel Field-Effect Transistors (TFETs)," International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, pp. 701-702, Sep. 26-29, 2016.
[83] Jang Woo Lee, Jong Han Park and Woo Young Choi, “Triple-gate tunnel FETs encapsulated with an epitaxial layer for high current drivability," 2016 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Hakodate, Japan, pp. 454-457, Jul. 4-6, 2016.
[82] Yong Jun Kim, Hyug Su Kwon and Woo Young Choi, “Nonvolatile Nanoelectromechanical Memory Switches for Low-Power and High-Speed CMOS-NEM Hybrid Reconfigurbal Logic," 2016 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Hakodate, Japan, pp. 482-484, Jul. 4-6, 2016.
[81] Ho Moon Lee and Woo Young Choi, “Mutually-actuated-nano-electromechanical (MA-NEM) memory switches for low operation voltage," 2016 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Hakodate, Japan, pp. 380-382, Jul. 4-6, 2016.
[80] Sang Wan Kim, Heesauk Jhon and Woo Young Choi, “Miniature CMOS Low Noise Amplifier in 0.18-um Mixed-Signal (Twin-Well) CMOS Process," ITC-CSCC 2015, Seoul, Korea, pp. 40, Jun.29 - Jul. 2, 2015.
[79] Jang Woo Lee, and Woo Young Choi, “Random Telegraph Noise Model of Tunnel Field-Effect Transistors," Nano Korea 2015 Symposium, Seoul, Korea, pp. 67, Jul. 1-3, 2015.
[78] In Huh, and Woo Young Choi, “Effects of Source Doping Concentration on the Subthreshold Swing (SS) of Tunneling Field-Effect Transistors (TFETs)," Nano Korea 2015 Symposium, Seoul, Korea, pp. 65, Jul. 1-3, 2015.
[77] Jong Han Park, and Woo Young Choi, “Esaki-Tunneling-Assisted Tunnel Field-Effect Transistors (ETFETs) for Extremely-Low-Power Applications," Nano Korea 2015 Symposium, Seoul, Korea, pp. 65, Jul. 1-3, 2015.
[76] Sang Wan Kim, Seongjae Cho, Jand Hyun Kim, Byung-Gook Park, and Woo Young Choi, "Improvement of On-Off Ratio in Vertical Electron-Hole Bilayer Tunnel Field-Effect Transistors (V-EHBTFETs)," International Conference on Electronics, Information and Communication, Singapore, pp.367-377, Jan. 28-31, 2015.
[75] Tae-Ho Lee, Young-Jun Kwon, Jae-Gwan Kim, Sung-Kun Park, In-Wook Cho, Kyung-Dong Yoo, Ji-song Lim, Da-Som Kim, Woo Young Choi, and Gyu-Han Yoon, "Charge Trap Length Dependence and Transconductance Characteristics of a 2T SONOS Cell," 14th Non-Volatile Memory Technology Symposium (NVMTS 2014), Jeju, Korea. pp. 195-196 , Oct. 27-29, 2014.
[74] Sang Wan Kim, Woo Young Choi, Hyun Woo Kim, Jang Hyun Kim, Euyhwan Park, Junil Lee, Taehyung Park, and Byung-Gook Park, “Investigation on Transient Response in Tunnel Field-Effect Transistors (TFETs) Depending on Device Geometric Parameters,” NANO Korea, Seoul, Korea, p. P1401_080, Jul. 1-3, 2014.
[73] Sang Wan Kim, Woo Young Choi, Jang Hyun Kim, Hyun Woo Kim, Euyhwan Park, Junil Lee, Taehyung Park, and Byung-Gook Park, “Vertical Structured Electron-Hole Bilayer Tunnel Field-Effect Transistors (V-EHBTFETs) for Complementary Logic Applications,” NANO Korea, Seoul, Korea, p. P1401_079, Jul. 1-3, 2014.
[72] Jaesung Jo, Hyunjae Lee, Hyun-Yong Yu, Woo Young Choi, and Changhwan Shin, “Fabriciation of a Ferroelectric Capacitor for Sub-60mV/dec CMOS Devices," 2014 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Kanazawa, Japan, pp. 32-34, July. 1-3, 2014.
[71] Dasom Kim, Gyu Han Yun, and Woo Young Choi, “Influence of Electron and Hole Distribution on SONOS Memory Cells," 2014 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Kanazawa, Japan, pp. 93-95, July. 1-3, 2014.
[70] Wooyoung Cheon, and Woo Young Choi, “Nonvolatile Memory Applications of Tunneling Field-Effect Transistors," 2014 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Kanazawa, Japan, pp. 90-92, July. 1-3, 2014.
[69] Yong Jun Kim, Jun Geun Kang, Byungin Lee, Gyu-Seog Cho, Sung-Kye Park, and Woo Young Choi, "Abnormal Cell-to-Cell Interference of NAND Flash Memory," 2013 International Conference on Solid State Devices and Materials, Fukuoka, Japan, Sep. 25-27, 2013.
[68] Jae Hwan Han, Jiyong Song, and Woo Young Choi, “Stiction-Induced Release voltage Shift of Nano-Electro-Mechanical (NEM) Memory Cells," Nano Korea 2013 Symposium, Seoul, Korea, O1309-001, Jul. 10-12, 2013.
[67] Jae Hwan Han, Kwanyong Kim, and Woo Young Choi, “Interference of Nano-Electro-Mechanical Memory Cells," 2013 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Seoul, Korea, pp. 143-144, Jun. 26-28, 2013.
[66] Sang Wan Kim, Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, and Byung-Gook Park, “Threshold voltage adjustment method of tunneling field-effect transistors”, International Conference on Electronics, Information and Communication (ICEIC), Bali, Indonesia, pp. 247-248, Jan. 30-Feb. 2, 2013.
[65] [Invited] Woo Young Choi, "Tunneling Field-Effect Transistors for Sub-0.5-V Operation," SEMICON Korea 2013 - SEMI Technology Symposium (STS), Seoul, Korea, p. S3-3, Jan. 30-31, 2013.
[64] Jae Hwan Han, Jiyong Song, and Woo Young Choi, "Investigation of Stiction Effects in Nano-Electro-Mechanical (NEM) Memory Cells Based on Finite Element Analysis (FEA)," 12th Non-Volatile Memory Technology Symposium (NVMTS 2012), Sentosa, Singapore. pp. 101-102 , Oct. 31- Nov. 2, 2012.
[63] Jun Geun Kang, Boram Han, Kyoung-Rok Han, Sung Jae Chung, Gyu-Seog Cho,Sung-Kye Park, and Woo Young Choi, "Dependency of NAND Flash Memory Cells on Random Dopant Fluctuation (RDF) Effects," 12th Non-Volatile Memory Technology Symposium (NVMTS 2012), Sentosa, Singapore. pp. 107-108 , Oct. 31- Nov. 2, 2012.
[62] Sang Wan Kim, Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, and Byung-Gook Park, "Design improvement of L-shaped tunneling field-effect transistors," IEEE International SOI Conference, pp. 4.1-, Oct. 2012.
[61] Sang Wan Kim, Woo Young Choi, Won Bo Shim, Hyungjin Kim, Min-Chul Sun, Hyun Woo Kim, and Byung-Gook Park, "Study on the ambipolar behavior depending on the length of gate-drain overlap," International Technical Conference on Circuits/Systems, Computers and Communications, pp. P-T3-09-, Jul. 2012.
[60] Sang Wan Kim, Woo Young Choi, Hyungjin Kim, Min-Chul Sun, Hyun Woo Kim, and Byung-Gook Park, "Investigation on hump effects of L-shaped tunneling field-effect transistors," Silicon Nanoelectronics Workshop, pp. 169-170, Jun. 2012.
[59] Min Su Han, Yeong Hwan Kim, Kyung Soo Kim, Jae Min Lee, Youngcheol Oh, Woo Young Choi, and Il Hwan Cho, “Modeling of Triangular Sacrificial Layer Residue Effect in Nano-Electro-Mechanical Nonvolatile Memory," 2012 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Okinawa, Japan, pp. 183-185, Jun. 27-29, 2012.
[58] Sang Wan Kim, Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, and Byung-Gook Park, "Investigation and optimization of the n-channel and p-channel L-shaped tunneling field-effect transistors," Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Okinawa, Japan, pp. 36-37, Jun. 27-29, 2012.
[57] Jun Geun Kang, Boram Han, Chung Sung Jae, Seok-Kiu Lee, Sung-Kye Park, Gyu-Seog Cho, Kyoung-Rok Han and Woo Young
Choi, “Effects of Random Dopant Fluctuations on NAND Flash Memory Cells,” 2012 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Okinawa, Japan, pp. 48-49, Jun. 27-29, 2012.
[56] Sang Wan Kim, Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, "Ambipolar Behabior of L-shaped Tunneling Field-Effect Transistros," International Conference on Electronics, Information and Communication, pp. 285-286, Feb. 1-3, 2012.
[55] Sang Wan Kim, Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, "L-Shaped Tunneling Field-Effect Transistors (TFETs) for Low Subthreshold Swing and High Current Drivability," 24th International Microprocesses and Nanotechnology Conference, Kyoto, Japan, pp. 26C-4-5L, Oct. 24-27, 2011.
[54] Jae Sung Lee, Woo Young Choi, and In Man Kang, "Characteristics of Gate-All-Around Hetero-Gate-Dielectric Tunneling FETs," 24th International Microprocesses and Nanotechnology Conference, Kyoto, Japan, pp. 26C-4-6, Oct. 24-27, 2011.
[53] [Invited] Woo Young Choi, "Nano-Electromechanical (NEM) Memory Cells for Highly Energy-Efficient Systems," IEEE Nanotechnology Materials and Devices Conference 2011, Jeju, Korea, pp. 32-37, Oct. 18-21, 2011.
[52] Gibong Lee and Woo Young Choi, "Low-Power Circuit Applicability of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors (HG TFETs)," 2011 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Daejeon, Korea, pp. 84-86, Jun. 29-Jul. 1, 2011.
[51] Boram Han and Woo Young Choi, "Analysis of Model of Fringe Field Effect in Nano-Electromechanical (NEM) Nonvolatile Memory," 2011 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Daejeon, Korea, pp. 277-279, Jun. 29-Jul. 1, 2011.
[50] [Invited] Woo Young Choi, "Nano-Electromechanical (NEM) Nonvolatile Memory for Low-Power Electronics," 2010 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Tokyo, Japan, pp. 5-6, Jun. 30 - Jul. 2, 2010.
[49] Min Jin Lee and Woo Young Choi, "Investigation of Abnormal Drain Current Increase of Tunneling Field-Effect Transistors," 2010 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Tokyo, Japan, pp. 55-56, Jun. 30 - Jul. 2, 2010.
[48] Seung Hyeun Roh and Woo Young Choi, "New Method for Evaluating the Scaling Trend of Nano-Electro-Mechanical (NEM) Nonvolatile Memory Cells," 2010 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Tokyo, Japan, pp. 231-232, Jun. 30 - Jul. 2, 2010.
[47] Kwangseok Lee and Woo Young Choi, "Multi-Bit Electromechanical Memory Cell for Simple Fabrication Process," IEEE 2010 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 47-48, Jun. 13-14, 2010.
[46] Jung-Shik Jang and Woo Young Choi, "Ambipolarity Characterization of Tunneling Field-Effect Transistors," IEEE 2010 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 135-136, Jun. 13-14, 2010.
[45] Woo Young Choi, "Comparative Study of Tunnel FETs and MOSFETs for Low-Power Consumption," 2009 International Conference on Solid State Devices and Materials, Sendai, Japan, Oct. 7-9, 2009.
[44] Woojun Lee and Woo Young Choi, "Quantitative Analysis of Hump Effects of Multi-Gate MOSFETs for Low-Power Electronics," 2009 International Conference on Solid State Devices and Materials, Sendai, Japan, Oct. 7-9, 2009.
[43] Woojun Lee and Woo Young Choi, "Novel Capacitorless DRAM Cell for Low Voltage Operation and Long Data Retention Time," 2009 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Busan, Korea, 3B.6, Jun. 24-26, 2009.
[42] Woojun Lee and Woo Young Choi, "A Novel Capacitorless 1T DRAM Cell for Data Retention Time Improvement," IEEE 2009 Silicon Nanoelectronics Workshop, Kyoto, Japan, pp. 67-68, Jun. 13-14, 2009.
[41] Woo Young Choi, Hei Kam, Donovan Lee, Joanna Lai, and Tsu-Jae King Liu, “Compact Nano-Electro-Mechanical Non-Volatile Memory (NEMory) for 3D Integration,” International Electron Devices Meeting (IEDM), Washington, DC, USA, pp. 603-606, Dec. 10-12, 2007.
[40] Jong Pil Kim, Jae Young Song, Sang Wan Kim, Woo Young Choi, Jong Duk Lee, and Byung-Gook Park, "30-nm Asymmetric NMOSFET Using a Novel Fabrication Method", IEEE 2007 Silicon Nanoelectronics Workshop, Kyoto, Japan, pp. 89-90, Jun. 10-11, 2007.
[39] Sang Wan Kim, Woo Young Choi, Jae Young Song, Jong Pil Kim, Junsoo Kim, Hyoungsoo Ko, Hongsik Park, Chulmin Park, Seungbum Hong, Sung-Hoon Choa, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park, "Analysis and Modeling of Resistive Probes", IEEE Nanotechnology Materials and Devices Conference 2006, Gyeongju, Korea, pp. 318-319, Oct. 22-25, 2006.
[38] Woo Young Choi, Jae Young Song, Jong Pil Kim, Sang Wan Kim, Jong Duk Lee, and Byung-Gook Park, "Breakdown Voltage Reduction in I-MOS Devices", IEEE Nanotechnology Materials and Devices Conference 2006, Gyeongju, Korea, pp. 380-381, Oct. 22-25, 2006.
[37] Hoon Jeong, Yeun Seung Lee, Sangwoo Kang, Il Han Park, Woo Young Choi, Hyungcheol Shin, Jong Duk Lee, and Byung-Gook Park, "Capacitorless DRAM Cell with Highly Scalable Surrounding Gate Structure," 2006 International Conference on Solid State Devices and Materials, pp.574-575, Yokohama, Japan, Sep. 13-15, 2006.
[36] Woo Young Choi, Jae Young Song, Jong Pil Kim, Jong Duk Lee, and Byung-Gook Park, "Multi-Functionality of Novel Structured Tunneling Devices," 2006 International Conference on Solid State Devices and Materials, pp.824-825, Yokohama, Japan, Sep. 13-15, 2006.
[35] Jae Young Song, Woo Young Choi, Jong Pil Kim, Jong Duk Lee, and Byung-Gook Park, "Novel Gate-All-Around MOSFETs with Self-Aligned Structure," 2006 International Conference on Solid State Devices and Materials, pp.1072-1073, Yokohama, Japan, Sep. 13-15, 2006.
[34] [Invited] Byung-Gook Park, Woo Young Choi, Kyung Rok Kim,"Inter-band tunneling and its application to nanoscale silicon devices : TFET, FITET and MOSFET," International Symposium on the Physics of Semiconductors and Applications 2006, Jeju, Korea, pp.10, Aug. 22-25, 2006.
[33] [Invited] Byung-Gook Park, Woo Young Choi, and Jong Duk Lee,"Characterization and Design Consideration of I-MOS Devices," International Technical Conference on Circuits/Systems, Computers and Communications 2006,Thailand, pp. III_693-III_696, Jul. 10-13, 2006.
[32] Kwon-chil Kang, Sangwoo Kang, Jin Ho Kim, Hong Sun Yang, Woo Young Choi, Gil Seong Lee, Jong Duk Lee, and Byung-Gook Park, "An Approach to a Small Dot Fabricated with an Etch-back Process," International Technical Conference on Circuits/Systems, Computers and Communications 2006,Thailand, pp. I_37-I_40, Jul. 10-13, 2006.
[31] Jong Pil Kim, Woo Young Choi, Jae Young Song, Seongjae Cho, Sangwoo Kang, Sang Wan Kim, Jong Duk Lee, and Byung-Gook Park, "Design and Simulation of Asymmetric MOSFETs," 2006 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Japan, pp. 175-178, Jul. 3-5, 2006.
[30] Jae Young Song, Woo Young Choi, Jong Pil Kim, Sang Wan Kim, Doo-Hyun Kim, Jin Ho Kim, Dong-Wook Park, Jong Duk Lee, and Byung-Gook Park, "Effects on Multi-Fin on Self-Aligned Gate-All-Around MOSFETs," 2006, Mongolia, pp. 21-24, Jun. 27-28, 2006.
[29] Ju Hee Park, Woo Young Choi, Jae Young Song, Jong Pil Kim, Jong Duk Lee, and Byung-Gook Park, "Double-Gate SOI FinFETs Using Sidewall Multi-Line Patterning Technique,” IEEE 2006 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 145-146, Jun. 11-12, 2006.
[28] Jong Pil Kim, Woo Young Choi, Jae Young Song, Ju Hee Park, Jong Duk Lee, and Byung-Gook Park, "Design and Fabrication of Asymmetric MOSFETs Using a Sidewall Spacer,” IEEE 2006 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 139-140, Jun. 11-12, 2006.
[27] Jae Young Song, Woo Young Choi, Ju Hee Park, Jong Pil Kim, Jong Duk Lee, and Byung-Gook Park, "Effects of Oversized Bottom Gate in Self-Aligned Gate-All-Around MOSFET ,” IEEE 2006 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 47-48, Jun. 11-12, 2006.
[26] Woo Young Choi, Byung Yong Choi, Ju Hee Park, Dong-Won Kim, Choong-Ho Lee, Donggun Park, Jong Duk Lee, Young June Park, and Byung-Gook Park, "25nm Programmable Virtual Source/Drain MOSFETs Using a Twin SONOS Memory Structure," International Semiconductor Device Research Symposium, Bethesda, U.S.A., Dec. 7~9, 2005.
[25] Woo Young Choi, Jae Young Song, Jong Duk Lee, Young June Park, and Byung-Gook Park, "70-nm Impact-Ionization Metal-Oxide-Semiconductor (I-MOS) Devices Integrated with Tunneling Field-Effect Transistors (TFETs)," International Electron Devices Meeting, Washington, DC, U.S.A., pp. 975-978, Dec. 5~7, 2005.
[24] Jong Duk Lee, Woo Young Choi, Byung-Gook Park, "Challenges in Nanoscale Devices and Breakthrough," 2005 IEEE National Symposium on Microelectronics,Kuching, Malaysia, pp. A1-A5, Nov. 21-24, 2005.
[23] Woo Young Choi, Jae Young Song, Ju Hee Park, Jong Duk Lee, Young June Park, and Byung-Gook Park, "Effect of Substrate Doping Concentration on I-MOS Characteristics," IEEE 2005 Silicon Nanoelectronics Workshop, Kyoto, Japan, pp. 46-47, Jun. 12-13, 2005.
[22] Jae Young Song, Woo Young Choi, JuHee Park, Jong Duk Lee, Young June Park, and Byung-Gook Park, "Optimization of GAA MOSFET Structure and Comparison with DG MOSFETs," IEEE 2005 Silicon Nanoelectronics Workshop, Kyoto, Japan, pp. 70-71, Jun. 12-13, 2005.
[21] Woo Young Choi, Jae Young Song, Byung Yong Choi, Jong Duk Lee, Young June Park, and Byung-Gook Park, "80nm Self-Aligned Complementary I-MOS Using Double Sidewall Spacer and Elevated Drain Structure and Its Applicability to Amplifiers with High Linearity," International Electron Devices Meeting, San Francisco, U.S.A., pp. 203-206, Dec. 13~15, 2004.
[20] Byung Yong Choi, Yong Kyu Lee, Woo Young Choi, Il Han Park, Hyungcheol Shin, Jong Duk Lee, Byung-Gook Park, Sung Taek Kang, Chilhee Chung, and Donggun Park, "Programmable Virtual Source/Drain MOSFETs," 34th European Soild-State Device Research Conference, Leuven, Belgium, pp. 229-232, Sep. 21-23, 2004.
[19] Byung Yong Choi, Yong-Kyu Lee, Woo Young Choi, Il Han Park, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "Nano-scale MOSFETs with Programmable Virtual Source/Drain,” 62nd Annual Device Research Conference, pp. 213-214, Indiana, USA, Jun. 21-23, 2004.
[18] Woo Young Choi, Byung Yong Choi, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "A New Fabrication Method for Self-aligned Nanoscale I-MOS (Impact-ionization MOS),” 62nd Annual Device Research Conference, pp. 211-212, Indiana, USA, Jun. 21-23, 2004.
[17] Woo Young Choi, Dong-Soo Woo, Byung Yong Choi, Jong Duk Lee, and Byung-Gook Park, "A Novel Biasing Scheme for the I-MOS (Impact-Ionization MOS),” IEEE 2004 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 61-62, Jun. 13-14, 2004.
[16] Byung Yong Choi, Woo Young Choi, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "INverted-Sidewall and Partially-Etched Channel (INSPEC) MOSFET on Fully Depleted SOI Substrates,” IEEE 2004 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 31-32, Jun. 13-14, 2004.
[15] Woo Young Choi, Byung Yong Choi, Dong-Soo Woo, Myeong Won Lee, Jong Duk Lee, and Byung-Gook Park, "A New Stable Extraction of Threshold Voltage Using Regularization Method," Int'l Conf. on Solid State Devices and Materials 2003, pp.420-421,Tokyo, Japan, Sep. 16-18, 2003.
[14] Woo Young Choi, Jong Duk Lee, Byung-Gook Park, "Reverse-Order Source/Drain Formation with Double Offset Spacer (RODOS) for CMOS Low-power, High-Speed and Low-Noise Amplifiers," 2003 International Symposium on Low Power Electronics and Design (ISLPED 2003), pp.189-192, Seoul, Korea, Aug. 25-27, 2003.
[13] Woo Young Choi, Byung Yong Choi, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "Reverse-Order Source/Drain with Double Offset Spacer (RODOS) for Sub-50nm Low-Power and High-Speed MOSFET Design," 2003 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Busan, Korea, pp. 5-8, Jun. 30-Jul. 2, 2003.
[12] Myeong Won Lee, In Man Kang, Byung Yong Choi, Dong-Soo Woo, Woo Young Choi, Jong Duk Lee, and Byung-Gook Park, "Juncion Leakage Characteristics of Shallow Trench Isolation (STI) with Nitrogen Pile-Up Sidewall Oxide," 2003 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Busan, Korea, pp. 5-8, Jun 30-Jul. 2, 2003.
[11] Dong-Soo Woo, Byung Yong Choi, Woo Young Choi, Jong Duk Lee, and Byung-Gook Park, "Self-Aligned FinFET with Large Source/Drain Fan-Out Strucure", IEEE 2003 Silicon Nanoelectronics Workshop, Kyoto, Japan, pp. 22-23, Jun. 8-9, 2003.
[10] Woo Young Choi, Byung Yong Choi, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "Sub-50nm MOSFET with Reverse-Order Source/Drain with Double Offset Spacer (RODOS)”, IEEE 2003 Silicon Nanoelectronics Workshop, Kyoto, Japan, pp. 22-23,Jun. 8-9, 2003.
[9] Woo Young Choi, Byung Yong Choi, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "A New Linearity Measurement Algorithm for Sub-Micron Microwave CMOS," 20th IEEE Instrumentation and Measurement Technology Conference, Vail Colorado, USA, pp. 374-376, May 20-22, 2003.
[8] Woo Young Choi, Byung Yong Choi, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "Stable Extraction of Threshold Voltage Using Transconductance Change Method," 203rd ECS Meeting, Paris, France, Abstract # 27, Apr. 27-May 2, 2003.
[7] Jong Duk Lee, Woo Young Choi, Byung Yong Choi, Young Jin Choi, Dong-Soo Woo, and Byung-Gook Park, "30 nm MOSFET Development Based on Processes for Nanotechnology," 2002 IEEE International Conference on Semiconductor Electronics (ICSE2002), pp. 251-254, Penang, Malaysia, Dec. 19-21, 2002.
[6] Dong-Soo Woo, Jong-Ho Lee, Woo Young Choi, Byung-Yong Choi, Young-Jin Choi, Jong Duk Lee, and Byung-Gook Park, "Electrical Characteristics of of FinFET with Vertically Non-Uniform S/D Doping Profile”, IEEE 2002 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 23-24, Jun. 9-10, 2002.
[5] Young Jin Choi, Byung Yong Choi, Dong-Soo Woo, Kyung Rok Kim, Woo Young Choi, Cheon Ahn Lee, Jong Duk Lee, and Byung-Gook Park, "A New Side-gate nMOSFET with 50nm Gate Length”, IEEE 2002 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 13-14, Jun. 9-10, 2002.
[4] Woo Young Choi, Byung Yong Choi, Jong Duk Lee, and Byung-Gook Park, "Side-Gate Design for 50nm Electrically Induced Source/Drain MOSFETs," Int'l Conf. on Solid State Devices and Materials 2001, pp.154-155, Tokyo, Japan, Sep. 26-28, 2001.
[3] Byung Yong Choi, Woo Young Choi, Young Jin Choi, Jong Duk Lee, and Byung-Gook Park, "Design of 50nm MOSFETs with Biased Side-Gates," 31th European Solid-State Device Research Conference, pp.287-290, Nuremberg, Germany, Sep. 11-13, 2001.
[2] Woo Young Choi, Suk Kang Sung, Kyung Rok Kim, Jong Duk Lee, and Byung-Gook Park, ”Nanoscale Poly-Si Line Formation and Its Uniformity,” 2001 Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices, pp. 11-16, Cheju, Korea, Jul. 4-7, 2001.
[1] Byung Yong Choi, Woo Young Choi, Young Jin Choi, Jong Duk Lee, and Byung-Gook Park, "Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs,” 2001 Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices, pp. 49-54, Cheju, Korea, Jul. 4-7, 2001.
Domestic
[118] Kyu-Ho Lee, Woo Young Choi, and Jong-Ho Lee, "Operation Principle of Reconfigurable Integrate-and-Fire Neuron Circuit", The 31st Korean Conference on Semiconductors, Gyeongju, Korea, p. 1368, Jan. 24-26, 2024.
[117] Kangwook Choi, Gyuweon Jung, Wonjun Shin,Jinwoo Park, Chayoung Lee, Donghee Kim, Hunhee Shin, Woo Young Choi, and Jong-Ho Lee, "Enhancement of Gas Sensing Performance in CuO Resistor-type Gas Sensors via Pre-Bias Voltage", The 31st Korean Conference on Semiconductors, Gyeongju, Korea, p. 646, Jan. 24-26, 2024.
[116] Subaek Lee, Sungjoon Kim, Hyojin So, Gyeongpyo Kim, Doohyung Kim, Minkang Kim, Juri Kim, Hyesung Nah, Woo Young Choi and Sungjun Kim, "Fabrication and Resistive Switching Characterization of HfOx-based 4-layer VRRAM for High-density Synapse Array", The 31st Korean Conference on Semiconductors, Gyeongju, Korea, p. 109, Jan. 24-26, 2024.
[115] Jin Wook Lee and Woo Young Choi, "Switching Voltage Analysis of Nanoelectromechanical Memory Switches", The 31st Korean Conference on Semiconductors, Gyeongju, Korea, p. 719, Jan. 24-26, 2024.
[114] Geun Tae Park and Woo Young Choi, "Binary Neural Networks Using Nanoelectromechanical Memory Switches", The 31st Korean Conference on Semiconductors, Gyeongju, Korea, p. 718, Jan. 24-26, 2024.
[113] 이선호, 박창헌, 노형준, 최우영, "터널 전계 효과 트랜지스터 기반 비휘발성 메모리," 제6회 반도체공학회 종합학술대회, Seoul, Korea, p. 6, Dec. 1, 2023.
[112] 염재민, 류민정, 최우영, "SiGe을 이용한 MFMIS TFETs의 performance 향상," 제6회 반도체공학회 종합학술대회, Seoul, Korea, p. 6, Dec. 1, 2023.
[111] 엄세현, 장진호, 최우영, "Interference 억제를 위한 Vertical NAND 구조," 제6회 반도체공학회 종합학술대회, Seoul, Korea, p. 6, Dec. 1, 2023.
[110] 한승현, 최우영, "강유전체 터널링 전계효과 트랜지스터의 불규칙 변이 분석," 제6회 반도체공학회 종합학술대회, Seoul, Korea, p. 4, Dec. 1, 2023.
[109] 박창헌, 최우영, "전하저장형 터널링 트랜지스터의 최적화," 제6회 반도체공학회 종합학술대회, Seoul, Korea, p. 6, Dec. 1, 2023.
[108] 류민정, 최우영, "강유전체 터널링 전계효과 트랜지스터 기반 인-메모리 컴퓨팅," 제6회 반도체공학회 종합학술대회, Seoul, Korea, p. 6, Dec. 1, 2023.
[107] 박종혁, 최우영, "하드웨어 기반 스파이킹 뉴럴 네트워크 구현을 위한 뉴런 회로," 제6회 반도체공학회 종합학술대회, Seoul, Korea, p. 5, Dec. 1, 2023.
[106] 김연우, 최우영, "AND-형 시냅스 어레이의 전류 미러링 방법," 제6회 반도체공학회 종합학술대회, Seoul, Korea, p. 4, Dec. 1, 2023.
[105] 김창하, 김동오, 최우영, "강유전체 전계 효과 트랜지스터에서의 게이트-소스/드레인 오버랩 영역의 도핑 농도 영향 분석," 제6회 반도체공학회 종합학술대회, Seoul, Korea, p. 4, Dec. 1, 2023.
[104] Joon Hwang, Min-Kyu Park, Won-Mook Kang, Woo Young Choi, and Jong-Ho Lee, "Effects of Inverter Circuit Size on Analog Pulse-Width Modulation Circuit," The 30th Korean Conference on Semiconductors, Jeongseon, Korea, p. 1013, Feb. 13-15, 2023.
[103] Kangwook Choi, Gyuweon Jung, Seongbin Hong, Yujeong Jeong, Wonjun Shin, Jinwoo Park, Donghee Kim, Hunhee Shin, Woo Young Choi, and Jong-Ho Lee, "NO2 Gas Response Improvement of Gas Sensors by Adopting Oxygen Vacancy Controlled In2O3 Bilayer Sensing Films," The 30th Korean Conference on Semiconductors, Jeongseon, Korea, p. 120, Feb. 13-15, 2023.
[102] Seongbin Oh, Woo Young Choi and Jong-Ho Lee, "Synaptic Devices Based on 3D-Semicircular NAND Flash Memory," The 30th Korean Conference on Semiconductors, Jeongseon, Korea, p. 782, Feb. 13-15, 2023.
[101] Kyungchul Park, Sungjoon Kim, and Woo Young Choi, "A Weight Split Method of RRAM Arrays for Neuromorphic Applications," The 30th Korean Conference on Semiconductors, Jeongseon, Korea, p. 384, Feb. 13-15, 2023.
[100] Yeonwoo Kim, Donghyun Ryu, and Woo Young Choi, "Analysis of the Current Mirroring Method for Accurate AND-Type Hardware-Based Neural Network Systems," The 30th Korean Conference on Semiconductors, Jeongseon, Korea, p. 531, Feb. 13-15, 2023.
[99] Jonghyuk Park, Kyungchul Park and Woo Young Choi, "Compensation-Circuit-Added Current Mirror for SNN accuracy Improvement," The 30th Korean Conference on Semiconductors, Jeongseon, Korea, p. 532, Feb. 13-15, 2023.
[98] Changha Kim, Dong-Oh Kim, Hyun-Min Kim, and Woo Young Choi, "Influence of Gate-Source/Drain Overlap Length on MFMIS FeFETs," The 30th Korean Conference on Semiconductors, Jeongseon, Korea, p. 132, Feb. 13-15, 2023.
[97] Junsu Yu, Sungmin Hwang, Taejin Jang, and Woo Young Choi, "Influence of Weight Transfer Error on Vector-Matrix Multiplication Operation," The 30th Korean Conference on Semiconductors, Jeongseon, Korea, p. 533, Feb. 13-15, 2023.
[96] Dong-Oh Kim, Changha Kim, Hyun-Min Kim, and Woo Young Choi, "Junctionless Ferroelectric-Metal Field-Effect Transistors (JL FeMFETs)," The 30th Korean Conference on Semiconductors, Jeongseon, Korea, p. 764, Feb. 13-15, 2023.
[95] Donghyun Ryu, Yeonwoo Kim, and Woo Young Choi, "Poly-Si Channel Flash Memory-Based Synaptic Devices for Spiking Neural Networks," The 30th Korean Conference on Semiconductors, Jeongseon, Korea, p. 383, Feb. 13-15, 2023.
[94] Sungjoon Kim, Kyungho Hong, Tae-Hyeon Kim, Yeon Joon Choi, and Woo Young Choi, "RRAM Array with a Pristine Low Resistance State," The 30th Korean Conference on Semiconductors, Jeongseon, Korea, p. 104, Feb. 13-15, 2023.
[93] Kyungho Hong, Sungjoon Kim, Tae-Hyeon Kim, and Woo Young Choi, "RRAM Reset Voltage Control Using Forming Gas Annealing," The 30th Korean Conference on Semiconductors, Jeongseon, Korea, p. 108, Feb. 13-15, 2023.
[92] Bosung Jeon, Taejin Jang, Junsu Yu, and Woo Young Choi, "Self-Aligned Asymmetric Double-Gate (SA-ADG) Synaptic Transistors for Neuromorphic Systems," The 30th Korean Conference on Semiconductors, Jeongseon, Korea, p. 763, Feb. 13-15, 2023.
[91] Yeon-Joon Choi, Tae-Hyeon Kim, Kyungho Hong, Sungjoon Kim, Sungjun Kim, and Woo Young Choi, "Self-Compliance Effects of the SiOx/SiNy Bilayer in Co CBRAM," The 30th Korean Conference on Semiconductors, Jeongseon, Korea, p. 101, Feb. 13-15, 2023.
[90] Min Jeong Ryu and Woo Young Choi, "Effect of Ge Mole Fraction on the Ambipolar Behavior of Si1-xGex Tunnel Field-Effect Transistors", The 30th Korean Conference on Semiconductors, Jeongseon, Korea, p. 768, Feb. 13-15, 2023.
[89] Jin Wook Lee, Jae Seong Lee, and Woo Young Choi, "Nearest Neighbor Search Using Nanoelectromechanical (NEM) Memory Switch-Based Content-Addressable Memory", The 30th Korean Conference on Semiconductors, Jeongseon, Korea, p. 296, Feb. 13-15, 2023.
[88] Geun Tae Park, Jae Seong Lee, and Woo Young Choi, "Ternary Content-Addressable Memory (TCAM) Using Nanoelectromechanical (NEM) Memory Switches", The 30th Korean Conference on Semiconductors, Jeongseon, Korea, p. 302 Feb. 13-15, 2023.
[87] Chang Heon Park and Woo Young Choi, "Tunnel Field-Effect Transistor-Based Charge Trapping Memory for In-Memory Computing", The 30th Korean Conference on Semiconductors, Jeongseon, Korea, p. 779, Feb. 13-15, 2023.
[86] Jae Seung Woo and Woo Young Choi, "Performance Enhancement Method of Line Tunnel Field-Effect Transistor (TFET) Using Hot Carrier Degradation", The 30th Korean Conference on Semiconductors, Jeongseon, Korea, p. 535, Feb. 13-15, 2023.
[85] Jang Woo Lee, Jae Seung Woo, and Woo Young Choi, "Temperature Dependence of SONOS Tunnel Field-Effect Transistors", The 29th Korean Conference on Semiconductors, Jeongseon, Korea, p. 52, Jan. 24-26, 2022.
[84] Hyug Su Kwon and Woo Young Choi, "Performance Comparison of Monolithic Three-Dimensional (M3D) Nanoelectromechanical (NEM) Memory Switches", The 29th Korean Conference on Semiconductors, Jeongseon, Korea, p. 113, Jan. 24-26, 2022.
[83] Jae Seung Woo, Kyung Min Koo, and Woo Young Choi, "Gate-Normal Charge Trapped (GCT) Tunnel Field-Effect Transistors (TFETs)", The 29th Korean Conference on Semiconductors, Jeongseon, Korea, p. 151, Jan. 24-26, 2022.
[82] Jae Seong Lee and Woo Young Choi, "Nanoelectromechanical-Switch-Based Ternary Content-Addressable Memory (NEMTCAM)", The 29th Korean Conference on Semiconductors, Jeongseon, Korea, p. 113, Jan. 24-26, 2022.
[81] Hyeontae Bang, Sangjun Lee, Jae Seung Woo, and Woo Young Choi, "Nanoelectromechanical Memory Switches for Binary Neural Networks", The 29th Korean Conference on Semiconductors, Jeongseon, Korea, p. 140, Jan. 24-26, 2022.
[80] Siyoun Lee, Seong-Yeon Kim, Haesoon Oh, Jaesung Sim, and Woo Young Choi, "Snapback Breakdown of MOSFETs Including Self-Heating Effects", The 29th Korean Conference on Semiconductors, Jeongseon, Korea, p. 52, Jan. 24-26, 2022.
[79] Jang Woo Lee, Jae Seung Woo, and Woo Young Choi, "SONOS 터널링 전계 효과 트랜지스터의 온도 의존성", 제4회 반도체공학회 종합학술대회, Seoul, Korea, pp. 2, Dec. 15, 2021.
[78] Gwangryeol Baek, Jisoo Yoon, and Woo Young Choi, " Tri-State Nanoelectromechanical Memory Switches", The 28th Korean Conference on Semiconductors, virtual, Korea, p. 750, Jan. 25-29, 2021.
[77] Hyug Su Kwon, and Woo Young Choi, "Tile-to-tile operation of monolithic three-dimensional (M3D) CMOS-Nanoelectromechanical (NEM) Reconfigurable Logic (RL)", The 28th Korean Conference on Semiconductors, virtual, Korea, p. 731, Jan. 25-29, 2021.
[76] Jae Seung Woo, Jang Woo Lee and Woo Young Choi, "Hot Carrirer Injection Analysis of Tunnel Field Effect Transistors", The 28th Korean Conference on Semiconductors, virtual, Korea, p. 231, Jan. 25-29, 2021.
[75] Kyung Min Koo, Woo Young Chung, Sang Yi Lee, Gyu Han Yoon, and Woo Young Choi, "Modeling of Statistical Variation Effects on DRAM Sense Amplifier Offset Voltage", The 28th Korean Conference on Semiconductors, virtual, Korea, p. 231, Jan. 25-29, 2021.
[74] Jae Seong Lee, and Woo Young Choi, "Content-Addressable Memory (CAM) Based on Nanoelectromechanical (NEM) Memory Switches for Low-Energy and High Speed Operation", The 28th Korean Conference on Semiconductors, virtual, Korea, p. 231, Jan. 25-29, 2021.
[73] Ha Rim Jeon, Yoon-Suk Kim, Uihui Kwon, and Woo Young Choi, "Compact Model of Metal-Ferroelectric-Insulator-Semiconductor (MFIS) Negative Capacitance FETs", The 28th Korean Conference on Semiconductors, virtual, Korea, p. 231, Jan. 25-29, 2021.
[72] Hyug Su Kwon and Woo Young Choi, "Monolithic three-dimensional CMOS-NEM Reconfigurable Logic for Island-style Operation", 제3회 반도체공학회 종합학술대회, Seoul, Korea, p. 12-2, Dec. 16th, 2020.
[71] Jae Seung Woo, Jang Woo Lee and Woo Young Choi, "Analysis of Hot Carrier Injection in Tunnel Field Effect Transistors", 제3회 반도체공학회 종합학술대회, Seoul, Korea, p. 12-3, Dec. 16th, 2020.
[70] Shinhee Kim, Jae Yeon Park, Hyug Su Kwon, Woo Young Choi and Sangwan Kim, "Low-Power Nanoelectromechanical(NEM) Device with HfO2-Based Ferroelectric Capacitor," The 27th Korean Conference on Semiconductors, Jeongseon, Korea, p. 624, Feb. 12-14, 2020.
[69] Min Hee Kang and Woo Young Choi, "Dynamic Slingshot Pull-In Operation of Nanoelectromechanical (NEM) Memory Switches for Low Operating Voltage", The 27th Korean Conference on Semiconductors, Jeongseon, Korea, p. 623, Feb. 12-14, 2020.
[68] Gwangryeol Baek and Woo Young Choi, "Novel Release Mechanism of Nanoelectromechanical Memory Switches", The 27th Korean Conference on Semiconductors, Jeongseon, Korea, p. 622, Feb. 12-14, 2020.
[67] Hyug Su Kwon, Ji Wang Ko, and Woo Young Choi, "Island-Style Monolithic Three-Dimensional (M3D) CMOS–NEM Reconfigurable Logic (RL) Circuits", The 27th Korean Conference on Semiconductors, Jeongseon, Korea, p. 621, Feb. 12-14, 2020.
[66] Min Hee Kang, Hyun Chan Jo, Hyug Su Kwon and Woo Young Choi, "Selection Line Optimization of Nanoelectromechanical (NEM) Memory Switches for Stress Relief", The 27th Korean Conference on Semiconductors, Jeongseon, Korea, p. 423, Feb. 12-14, 2020.
[65] Hyug Su Kwon and Woo Young Choi, "Monolithic three-dimensional (M3D) CMOS- Nanoelectromechanical (NEM) Single-tile Reconfigurable Logic (RL)", The 27th Korean Conference on Semiconductors, Jeongseon, Korea, p. 60, Feb. 12-14, 2020.
[64] Jae Seung Woo and Woo Young Choi, "Capacitorless Double-Gate PNPN TFET 1T DRAM with SiGe Channel", The 27th Korean Conference on Semiconductors, Jeongseon, Korea, p. 21, Feb. 12-14, 2020.
[63] Jang Woo Lee and Woo Young Choi, "A Novel Gate-Normal Hetero-Gate-Dielectric (GHG) Tunnel Field-Effect Transistors (TFETs)", The 27th Korean Conference on Semiconductors, Jeongseon, Korea, p. 20, Feb. 12-14, 2020.
[62] Jang Woo Lee and Woo Young Choi, "A Novel π-Shaped Gate-Normal Hetero-Gate-Dielectric (GHG) Tunnel Field-Effect Transistors (TFETs) ," 반도체공학회 학술대회, Seoul, Korea, p. 367, Dec. 18th, 2019.
[61] Ji Wang Ko and Woo Young Choi, "Advantages of Monolithic-3D (M3D) CMOS-nanoelectromechanical (CMOS-NEM) Reconfigurable Logic (RL) Circuits," 반도체공학회 학술대회, Seoul, Korea, p. 360, Dec. 18th, 2019.
[60] Gwangryeol Baek and Woo Young Choi, "Release Operation of Nanoelectromechanical (NEM) Switches," 반도체공학회 학술대회, Seoul, Korea, p. 355, Dec. 18th, 2019.
[59] Min Hee Kang and Woo Young Choi, "Slingshot Pull-in Operation of Nanoelectromechanical (NEM) Switches," 반도체공학회 학술대회, Seoul, Korea, p. 352, Dec. 18th, 2019.
[58] [Invited] Woo Young Choi, "에어갭 스마트 배선 기반 고속 저전력 내용 주소화 기억장치 소자 기술개발", 대한전자공학회 추계학술대회, Gangneung, Korea, p. 11, Nov. 22-23, 2019.
[57] Jang Woo Lee, Min Woo Kang, and Woo Young Choi, "Design Guideline of Tunnel FETs (TFETs) Considering Negative Differential Transconductance (NDT)", The 26th Korean Conference on Semiconductors, Hoengseong, Korea, p. 282, Feb. 13-15, 2019.
[56] Ho Moon Lee, Hyun Chan Jo, Hyug Su Kwon, and Woo Young Choi, "Switching Voltage Analysis of Nanoelectromechanical Memory Switches", The 26th Korean Conference on Semiconductors, Hoengseong, Korea, p. 596, Feb. 13-15, 2019.
[55] Hyug Su Kwon and Woo Young Choi, "CMOS-Nanoelectromechanical (NEM) Hybrid Circuits", The 26th Korean Conference on Semiconductors, Hoengseong, Korea, p. 597, Feb. 13-15, 2019.
[54] Ji Wang Ko and Woo Young Choi, " Monolithic-3D (M3D) CMOS-nanoelectromechanical (CMOS-NEM) Reconfigurable Logic (RL) Circuits", The 26th Korean Conference on Semiconductors, Hoengseong, Korea, p. 284, Feb. 13-15, 2019.
[53] Hyun Chan Jo, Min Hee Kang, and Woo Young Choi, "Nanoelectromechanical (NEM) Memory Switches with Notched Anchors for Low-Voltage Operation", The 26th Korean Conference on Semiconductors, Hoengseong, Korea, p. 281, Feb. 13-15, 2019.
[52] Seongun Shin, Gyuhan Yoon, Seon Young Cha, Seon Soon Kim, Kwang Ho Ahn, Woo Young Chung, Se Hyun Kim, and Woo Young Choi, "Reliability Modeling of DRAM Storage Capacitors", The 25th Korean Conference on Semiconductors, Jeongseon, Korea, p. 441, Feb. 5-7, 2018.
[51] Hyun Chan Jo and Woo Young Choi, "Novel Packaging Method of CMOS-Nano-Electromechanical (NEM) Hybrid Circuits", The 25th Korean Conference on Semiconductors, Jeongseon, Korea, p. 95, Feb. 5-7, 2018.
[50] Ho Moon Lee and Woo Young Choi, "Operating Voltage Analysis of CMOS-Nano-Electromechanical (NEM) Hybrid Circuits", The 25th Korean Conference on Semiconductors, Jeongseon, Korea, p. 94, Feb. 5-7, 2018.
[49] Hyug Su Kwon, Seung Kyu Kim, and Woo Young Choi, "Monolithic 3D CMOS-Nanoelectromechanical (NEM) Hybrid Circuits, Jeongseon, Korea, p. 93, Feb. 5-7, 2018.
[48] Jang Woo Lee and Woo Young Choi, "Investigation on Negative Differential Transconductance (NDT) of Double-Gate Tunnel FETs", The 25th Korean Conference on Semiconductors, Jeongseon, Korea, p. 460, Feb. 5-7, 2018.
[47] Sang Wan Kim, Woo Young Choi, Min-Chul Sun, and Byung-Gook Park, "Enhanced compact model for Ge-Si heterojunction double-gate tunnel field-effect transistors (TFETs)," NANO Korea, Goyang, Korea, pp. P1701_0654, Jul. 12-14, 2017.
[46] [Invited] Woo Young Choi, "Nano-Electromechanical (NEM) Devices for Extreme Environments," The Korean Physical Society (KPS) Spring Meeting, Daejeon, Korea, p.F2.04, Apr. 19-21, 2017.
[45] Ho Moon Lee and Woo Young Choi, "Release Voltage Modeling for Nano-Electromechanical (NEM) Memory Switches", Nano Convergence Conference2017, Seoul, Korea, p. 182 , Feb. 22-23, 2017.
[44] Tae Min Cha and Woo Young Choi, "Nano-Electromechanical-(NEM-) Memory-Based Field-Programmable Gate Arrays (FPGAs)", The 24th Korean Conference on Semiconductors, Hongcheon, Korea, p. 278 , Feb. 13-15, 2017.
[43] Tae Min Cha and Woo Young Choi, "Nano-Electromechanical (NEM) Relay Design Using CMOS Back-End-of-Line (BEOL) Process", The 24th Korean Conference on Semiconductors, Hongcheon, Korea, p. 278 , Feb. 13-15, 2017.
[42] In Huh and Woo Young Choi, "Influence of Temperature and Doping Concentration on the Energy Filtering Effects of Tunnel Field-Effect Transistors", The 24th Korean Conference on Semiconductors, Hongcheon, Korea, p. 33 , Feb. 13-15, 2017.
[41] Ho Moon Lee and Woo Young Choi, "Switching Voltage Modeling of Nano-Electromechanical (NEM) Memory Switches", The 24th Korean Conference on Semiconductors, Hongcheon, Korea, p. 32 , Feb. 13-15, 2017.
[40] Jang Woo Lee and Woo Young Choi, "Hump Effect of Triple-Gate Tunnel FETs Encapsulated with an Epitaxial Layer (EL TFETs)", The 24th Korean Conference on Semiconductors, Hongcheon, Korea, p. 15 , Feb. 13-15, 2017.
[39] Hyung Su Kwon, Sangmoo Choi, Sung-Yong Chung, Gyu-Seog Cho, Sung-Kye Park and Woo Young Choi, "Intercell Trapped Charge (ITC) Suppression of Vertical NAND (VNAND) Flash Memory", The 24th Korean Conference on Semiconductors, Hongcheon, Korea, p. 48 , Feb. 13-15, 2017.
[38] Heesauk Jhon and Woo Young Choi, "0.3-V supply Charge pump circuit for 65 nm CMOS", The 23th Korean Conference on Semiconductors, Jeongseon, Korea, p. 199 , Feb. 22-24, 2016.
[37] Seung Kyu Kim and Woo Young Choi, "Fabrication and Characteristics of Low-Power Device Switches", The 23th Korean Conference on Semiconductors, Jeongseon, Korea, p. 198 , Feb. 22-24, 2016.
[36] Seung Kyu Kim and Woo Young Choi, "Fabrication and Characteristics of Low-Power Device Inverters", The 23th Korean Conference on Semiconductors, Jeongseon, Korea, p. 198 , Feb. 22-24, 2016.
[35] Hyug Su Kwon, Hyunseung Yoo, Gyu-Seong Cho, Sung-Kye Park and Woo Young Choi, "Novel Degradation of Vertical NAND (VNAND) Flash Memory Cells", The 23th Korean Conference on Semiconductors, Jeongseon, Korea, p. 50 , Feb. 22-24, 2016.
[34] In Eui Lim, Heesauk Jhon, Gyuhan Yoon, Byung Kil Choi, Heung Sik Park, Seok Kiu Lee and Woo Young Choi, "Bias-Dependent On-Current Modeling of Ultra Short-Channel PMOSFETs with Hot-Carrier Stress Effects", The 23th Korean Conference on Semiconductors, Jeongseon, Korea, p. 20 , Feb. 22-24, 2016.
[33] Woo Young Cheon, Jangwoo Lee, and Woo Young Choi, "Improved Hetero-Gate-Dielectric Tunnel Field-Effect Transistors", The 23th Korean Conference on Semiconductors, Jeongseon, Korea, p. 18 , Feb. 22-24, 2016.
[32] [Invited] Woo Young Choi, "Next-Generation Electron Devices for Extremely-Low-Power Applications," Nano Convergence Conference, Seoul, Korea, p. 42 , Jan. 21-22, 2016.
[31] Kyung Min Choi, Seung Kyu Kim, and Woo Young Choi, "Work-function Variation and Random Dopand Fluctuation of Tunneling Field-Effect Transistros(TFETs)", The 22th Korean Conference on Semiconductors, Incheon, Korea, p. ? , Feb. 10-12, 2015.
[30] Jae Hwan Han, Yong Jun Kim, Tae Min Cha, and Woo Young Choi, "Zigzag Multi-Bit Nano-Electromechanical Memory Cells," The 22th Korean Conference on Semiconductors, Incheon, Korea, p. ? , Feb. 10-12, 2015.
[29] Woo Young Cheon, and Woo Young Choi, "Nonvolatile Memory Application of Tunneling Field-Effect Transistors," The 22th Korean Conference on Semiconductors, Incheon, Korea, p. ? , Feb. 10-12, 2015.
[28] Da Som Kim, Tae Ho Lee, Young Jun Kwon, Sung Kun Park, In Wook Cho, Kyung Dong Youu, Gyu Han Yun, and Woo Young Choi, "Influence of Electron and Hole Distribution on Embedded SONOS Nonvolatile Memory," The 22th Korean Conference on Semiconductors, Incheon, Korea, p. ? , Feb. 10-12, 2015.
[27] Yong Jun Kim, and Woo Young Choi, "Comparison between CMOS and Nano-Electromechanical (NEM) Switches," The 22th Korean Conference on Semiconductors, Incheon, Korea, p. ? , Feb. 10-12, 2015.
[26] Jae Hwan Han, Hyunjin Lee, Wansoo Kim, Gyuhan Yoon, and Woo Young Choi, "On-State Resistance Instability of Antifuses during Read Operation," The 21th Korean Conference on Semiconductors, Seoul, Korea, p. 431, Feb. 24-26, 2014.
[25] 임지송, 최우영, 윤규한, 이태호, 권영준, 박성근, 조인욱, 유경동, "2T-SONOS 셀의 Endurance 특성고찰," 대한전자공학회 하계종합학술대회, 제주시, 대한민국, pp. 88-91, Jul. 3-5, 2013.
[24] Hyun Kook Lee and Woo Young Choi, "Linearity Analysis of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors," The 20th Korean Conference on Semiconductors, Hoengseong, Korea, TH3-G-2, Feb, 4-6, 2013.
[23] Sang Wan Kim, Woo Young Choi, Min-Chul Sun, and Byung-Gook Park, "Study on the corner effect of L-shaped tunneling field-effect transistors," NANO Korea, pp. O1201_010-, Aug. 2012.
[22] Sang Wan Kim, Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, "터널링 장벽의 폭이 터널링 전계 효과 트랜지스터의 특성에 미치는 영향에 대한 연구," 하계종합학술대회, pp. 138-141, Jun. 27-29, 2012.
[21] [Invited] Woo Young Choi, "고에너지 효율 시스템 구현을 위한 나노전기기계 소자," 하계종합학술대회, pp. ix, Jun. 27-29, 2012.
[20] [Invited] Woo Young Choi, " Tunneling Field-Effect Transistors: The Next-Generation Devices," The 19th Korean Conference on Semiconductors, Seoul, Korea, p. 336, Feb. 15-17, 2012.
[19] Boram Han and Woo Young Choi, " Analysis of Fringe Field Effects in Nano-Electromechanical (NEM) Nonvolatile Memory Cells," The 19th Korean Conference on Semiconductors, Seoul, Korea, pp. 481-482, Feb. 15-17, 2012.
[18] Kwangseok Lee and Woo Young Choi, "Disturbance Characteristics of Nano-Electromechanical (NEM) Memory Cell (T Cell)," The 18th Korean Conference on Semiconductors, Jeju, Korea, pp. 518-519, Feb. 16-18, 2011.
[17] Seung Hyeun Roh and Woo Young Choi, "Scaling of Nano-Electro-Mechanical System (NEMS) Nonvolatile Memory Cells Based on Finite Element Analysis (FEA)," The 17th Korean Conference on Semiconductors, Daegu, Korea, pp. 288-289, Feb. 24-26, 2010.
[16] Woojun Lee and Woo Young Choi, "Hetero-Gate-Dielectric Tunneling Field-Effect Transistors (HG TFETs) for High Performance and Low-Power Consumption," The 17th Korean Conference on Semiconductors, Daegu, Korea, pp. 49-50, Feb. 24-26, 2010.
[15] Woo Young Choi, "Novel Electromechanical Nonvolatile Memory Cell (H Cell) for Multi-Bit Operation," The 17th Korean Conference on Semiconductors, Daegu, Korea, pp. 9-10, Feb. 24-26, 2010.
[14] Woo Young Choi, "Design Guideline and Scalability of Nano-Electro-Mechanical Non-Volatile Memory (NEMory) Cells," The 16th Korean Conference on Semiconductors, Daejeon, Korea, pp. 575-576, Feb. 19-20, 2009.
[13] [Invited] 최우영, "차세대 CMOS 소자," 2006년도 대한전자공학회 추계종합학술대회, 서울시, pp. 9-10, 11월 29일, 2008.
[12] 최우영, 송재영, 김종필, 김상완, 이종덕, 박병국, "Reduction of Breakdown Voltage in I-MOS Devices," 2006년도 대한전자공학회 하계종합학술대회, 제주도, pp. 593-594, 06월 21일-23일, 2006.
[11] 김종필, 최우영, 송재영, 김상완, 이종덕, 박병국, "Design and Simulation of Asymmetric MOSFETs," 2006년도 대한전자공학회 하계종합학술대회, 제주도, pp. 577-578, 06월 21일-23일, 2006.
[10] Woo Young Choi, Jae Young Song, Jong Pil Kim, Jong Duk Lee, and Byung-Gook Park, "I-MOS Devices with High ON/OFF Current Ratio and Its integration with TFETs," The 13th Korean Conference on Semiconductors, Jaeju Island, Korea, pp. 101-102, Feb. 23-24, 2006.
[9] Woo Young Choi, Jae Young Song, Ju Hee Park, Hoon Jung, Byung Yong Choi, Jong Duk Lee, Young Jun Park, and Byung-Gook Park, "Fabrication of a 100nm n-Channel I-MOS and Its Electrical Characteristics," The 12th Korean Conference on Semiconductors, Seoul, Korea, pp. 101-102, Feb. 24-25, 2005.
[8] H. S. Min, Y. J. Park, B. G. Park, S. Jin, W. Choi, S. Hong and R. Kim, "NANOCAD for Modeling and Simulation of Nano Scale and RF MOSFETs," The 1st Workshop on the Emerging Technologies of Semiconductors, Jeju, Korea, pp. 16-17, Oct. 21, 2004.
[7] W. Y. Choi and B.-G. Park, "20nm Planar nMOSFETs Using nanofabrication Technologies," The 1st Workshop on the Emerging Technologies of Semiconductors, Jeju, Korea, pp. 114-115, Oct. 21, 2004.
[6] Woo Young Choi, Hwi Kim, Dong-Soo Woo, Byung Yong Choi, Byoungho Lee, Jong Duk Lee, and Byung-Gook Park, "A New Stable Threshold Voltage Extraction Method Using the Regularization Theory," The 11th Korean Conference on Semiconductors, Seoul, Korea, vol. 2, pp. 205-206, Feb. 19-20, 2004.
[5] Dong-Soo Woo, Jihye Kong, Hyun Ho Kim, Woo Young Choi, Byung Yong Choi, Jong Duk Lee, Byung-Gook Park, "Low Resistance 30nm Self-Aligned FinFET," The 11th Korean Conference on Semiconductors, Seoul, Korea, vol. 2, pp. 203-204, Feb. 19-20, 2004.
[4] Woo Young Choi, Byung Yong Choi, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "Reverse-Order Source/Drain with Double Offset Spacer (RODOS) for Sub-50nm Low-Power and High-Speed MOSFET Design," The 10th Korean Conference on Semiconductors, Seoul, Korea, pp. 309-310, Feb. 27-28, 2003.
[3] Woo Young Choi, Byung Yong Choi, Young Jin Choi, Dong-Soo Woo, Suk-Kang Sung, Cheon An Lee, Kyung-Hoon Chung, Jong Duk Lee, and Byung-Gook Park, "Development of Ultra-Fine Process Technologies and Their Application to 30nm nMOSFETs," The 9th Korean Conference on Semiconductors, Chunan, Korea, pp. 61-62, Feb. 21-22, 2002.
[2] Young Jin Choi, Byung Yong Choi, Dong-Soo Woo, Kyung Rok Kim, Woo Young Choi, Cheon Ahn Lee, Jong Duk Lee, and Byung-Gook Park, "A New 50nm nMOSFET with Side-Gates for Virtual Source/Drain Extension," The 9th Korean Conference on Semiconductors, Chunan, Korea, pp. 65-66, Feb. 21-22, 2002.
[1] Dong Soo Woo, Jong Ho Lee, Woo Young Choi, Byung Yong Choi, Young Jin Choi, Jong Duk Lee, and Byung-Gook Park, "Design of Self-Aligned Double-Gate MOSFET with Low Source/Drain Resistance," The 9th Korean Conference on Semiconductors, Chunan, Korea, pp. 573-574, Feb. 21-22, 2002.