Journal
[190] Geun Tae Park, Jin Wook Lee, Jae Seung Woo, and Woo Young Choi, "XNOR Operation of Binary Neural Networks Using Nanoelectromechanical Memory Switches," IEEE Transactions on Electron Devices, To be published, [SCI] DOI : 10.1109/TED.2024.3486267
[189] Jin Wook Lee, Geun Tae Park, Myeong Su Shin, Woo Young Choi, "Torsional-Via-Assisted Nanoelectromechanical Memory Switches," IEEE Electron Device Letters, To be published, [SCI] DOI : 10.1109/LED.2024.3483752
[188] Gyuweon Jung, Kangwook Choi, Suyeon Ju, Jaehyeon Kim, Wonjun Shin, Seongi Lee, Gyuho Yeom, Ryun-Han Koo, Young-Chang Joo, Woo Young Choi, Seungwu Han, and Jong-Ho Lee*, "Chemisorption Manipulation by Adjusting the Carrier Concentration of the Adsorbent and Its Application to Adsorbate Identification", ACS Materials Letters, vol. 6, no. 10, pp 4783-4790, Sep. 2024. [SCI] DOI : 10.1021/acsmaterialslett.4c01729
[187] Sungjoon Kim, Hyeonseung Ji, Kyungchul Park, Hyojin So, Hyungjin Kim, Sungjun Kim*, and Woo Young Choi* "Memristive Architectures Exploiting Self-Compliance Multilevel Implementation on 1 kb Crossbar Arrays for Online and Offline Learning Neuromorphic Applications", ACS Nano, vol. 18, no. 36, pp 25128-25143, Aug. 2024. [SCI] DOI : 10.1021/acsnano.4c06942
[186] Sungjoon Kim, Hyeonseung Ji, Sungjun Kim,* and Woo Young Choi*, "Enhanced Reliability and Self-Compliance of Synaptic Arraysfor Multibit Encoded Neuromorphic Systems," Advanced Electronic Materials, To be published, [SCI] DOI : 10.1002/aelm.202400282
[185] Suhyeon Ahn, Junsu Yu, Hwiho Hwang, Min Suk Song, Dayeon Yu, Sungmin Hwang , In-Young Chung, Woo Young Choi , and Hyungjin Kim, "Coupling-Free Readout Scheme for Memcapacitors With NAND Flash Structure," IEEE Transcations on Electron Devices, vol. 71, no. 8, pp. 4670 - 4676, Aug. 2024., [SCI] DOI : 10.1109/TED.2024.3418289
[184] Junsu Yu, Donghyun Ryu, and Woo Young Choi, "A Novel Verification Method of Minimizing Verification Error in AND-Type Flash Arrays," IEEE Electron Device Letters, vol.45, no. 8, pp. 1472 - 1475, Aug. 2024., [SCI] DOI :10.1109/LED.2024.3416185
[183] Jiseong Im, Jangsaeng Kim, Joon Hwang, Minkyu Park, Ryun-Han Koo, Jonghyun Ko , Sung-Ho Park, Woo Young Choi, and Jong-Ho Lee, "Vertical AND-Type Flash TFT Array Capable of Accurate Vector-Matrix Multiplication Operations for Hardware Neural Networks," IEEE Electron Device Letters, vol. 45, no.7, pp. 1385 - 1388, Jul. 2024. [SCI] DOI : 10.1109/LED.2024.3406033
[182] Jangsaeng Kim, Jiseong Im, Wonjun Shin, Soochang Lee, Seongbin Oh, Dongseok Kwon, Gyuweon Jung, Woo Young Choi, and Jong-Ho Lee*, "Demonstration of In-Memory Biosignal Analysis: Novel High-Density and Low-Power 3D Flash Memory Array for Arrhythmia Detection", Advanced Science, vol. 11 , no. 26 , pp.2308460, Jul. 2024. [SCI] DOI : 10.1002/advs.202308460
[181] Kyungchul Park , Sungjoon Kim , Min-Hye Oh , Woo Young Choi * ,"Resting-potential-adjustable soft-reset integrate-and-fire neuron model for highly reliable and energy-efficient hardware-based spiking neural networks", Neurocomputing, vol.590, p.127762, Jul. 2024., [SCI] DOI :10.1016/j.neucom.2024.127762
[180] Jin Ho Chang, Jae Seung Woo, Suk-Kang Sung, Ki-Whan Song, and Woo Young Choi, "Ternary-State Vertical NAND Flash Memory for the Improvement of the Density and Accuracy of Quantized Neural Networks", IEEE Transactions on Electron Devices, vol. 71, no. 6, pp. 3985 - 3988, Jun. 2024. [SCI] DOI : 10.1109/TED.2024.3390651
[179] Joon Hwang, Min-Kyu Park, Won-Mook Kang, Ryun-Han Koo, Kyu-Ho Lee, Dongseok Kwon, Woo Young Choi, and Jong-Ho Lee, "NOR-Type Flash Array Based on Four-Terminal TFT Synaptic Devices Capable of Selective Program/Erase Exploiting Fowler-Nordheim Tunneling", IEEE Electron Device Letters, vol 45, no.6, pp. 1000 - 1003, Jun. 2024. [SCI] DOI : 10.1109/LED.2024.3388993
[178] Kangwook Choi, Gyuweon Jung, Wonjun Shin, Jinwoo Park, Chayoung Lee, Donghee Kim, Hunhee Shin, Woo Young Choi, and Jong-Ho Lee*, "NO2 gas response improvement method by adopting oxygen vacancy controlled In2O3 double sensing layers", Solid State Electronics, vol. 216, p. 108926, Jun. 2024., [SCI] DOI : 10.1016/j.sse.2024.108926
[177] Sungjoon Kim, Kyungho Hong, Hyungjin Kim, Min-Hwi Kim,* and Woo Young Choi*, "Overshoot-Suppressed Memristor Array with AlN OxygenBarrier for Low-Power Operation in the Intelligent Neuromorphic Systems", Advanced Intelligent Systems, vol. , no. , pp. 2300797, May 2024. [SCI] DOI : 10.1002/aisy.202300797
[176] Jin Wook Lee, Geun Tae Park, and Woo Young Choi, "Analytical Release Voltage Model of Monolithic 3-D Integrated Nanoelectromechanical Memory Switches", IEEE Transactions on Electron Devices, vol. 71, no. 5, pp. 3150-3155, May 2024. [SCI] DOI : 10.1109/TED.2024.3371939
[175] Sungjoon Kim, Kyungchul Park, Kyungho Hong, Tae-Hyeon Kim, Jinwoo Park, Sangwook Youn, Hyungjin Kim,* and Woo Young Choi* "Overshoot-Suppressed Memristor Crossbar Array with HighYield by AlOx Oxidation for Neuromorphic System," Advanced Materials Technology, vol. 9, no. 11, pp.2400063, Apr. 2024. [SCI] DOI : 10.1002/admt.202400063
[174] Kyungchul Park, Sungjoon Kim, Jong-Hyuk Park, and Woo Young Choi, "A Quantized-Weight-Splitting Method of RRAM Arrays for Neuromorphic Applications", IEEE Access, vol.12, pp. 59680-59687, Apr. 2024. [SCI] DOI: 10.1109/ACCESS.2024.3394253
[173] Changha Kim, Dong-Oh Kim, and Woo Young Choi, "Influence of gate-source/drain overlap on FeFETs", Solid State Electronics, vol. 214, p. 108862, Apr. 2024, [SCI] DOI:10.1016/j.sse.2024.108862
[172] Donghyun Ryu, Junsu Yu, and Woo Young Choi*, "Reverse Charge Injection Dual-Gate Synaptic Transistors for Effective Weight Update", IEEE Transactions on Nanotechnology, vol. 23, pp.217-222, Mar. 2024., [SCI] DOI: 10.1109/TNANO.2024.3371582
[171] Bosung Jeon, Seunghwan Song, Jae-Joon Kim, and Woo Young Choi, "Simultaneous Spike Processing for 3D NAND-Based Spiking Neural Networks," IEEE Electron Device Letters, vol. 45, no. 3, pp. 340-343, Mar. 2024. [SCI] DOI: 10.1109/LED.2024.3355889
[170] Kyungchul Park, Sungjoon Kim, Myung-Hyun Baek, Bosung Jeon, Yeon-Woo Kim, and Woo Young Choi, "Neurons with Captive Synaptic Devices for Temperature Robust Spiking Neural Networks", IEEE Electron Device Letters, vol. 45, no. 3, pp. 492-495, Mar. 2024. [SCI] DOI: 10.1109/LED.2023.3346755
[169] Minjeong Ryu and Woo Young Choi, "Surface Stoichiometry Dependence of Ambipolar SiGe Tunnel Field-effect Transistors and Its Effect on the Transient Performance Improvement," Journal of Semiconductor Technology and Science, vol. 24, no. 1, pp. 1-7, Feb. 2024. [SCI] DOI: 10.5573/JSTS.2024.24.1.1
[168] Jihyung Kim, Subaek Lee, Sungjoon Kim, Seyoung Yang, Jung-Kyu Lee, Tae-Hyeon Kim, Muhammad Ismail, Chandreswar Mahata, Yoon Kim, Woo Young Choi*, and Sungjun Kim*, "Synaptic Characteristics and Vector-Matrix Multiplication Operation in Highly Uniform and Cost-Effective Four-Layer Vertical RRAM Array," Advanced Functional Materials, vol. 34, no. 8, pp.2310193, Feb. 2024. [SCI] DOI: 10.1002/adfm.202310193
[167] Minjeong Ryu, Jae Seung Woo, Chae Lin Jung, and Woo Young Choi, "One-Transistor Ternary Content-Addressable Memory Based on Localized Ferroelectric Switching for Massive and Accurate Routing," IEEE Electron Device Letters, vol. 45, no. 2, pp. 144-147, Feb. 2024. [SCI] DOI: 10.1109/LED.2023.3345412
[166] Kyu-Ho Lee, Dongseok Kwon, In-Seok Lee, Joon Hwang, Jiseong Im, Jong-Ho Bae, Woo Young Choi, Sung Yun Woo, and Jong-Ho Lee, "Si-Based Dual-Gate Field-Effect Transistor Array for Low-Power On-Chip Trainable Hardware Neural Networks," Advanced Intelligent Systems, vol. 6, no. 1, p. 2300490, Jan. 2024. [SCI] DOI: 10.1002/aisy.202300490
[165] Joon Hwang, Ho-Nam Yoo, Kyu-Ho Lee, Jong-Won Back, Min-Kyu Park, Yeongheon Yang, Woo Young Choi, and Jong-Ho Lee, "Accurate SPICE Model for Cells With Tube-Type Poly-Si Channel in Cell Strings of Vertical NAND Flash Memory," IEEE Transactions on Electron Devices, vol. 70, no. 10, pp. 5469-5474, Oct. 2023. [SCI] DOI: 10.1109/TED.2023.3308086
[164] Jae Seung Woo, Chae Lin Jung, Ki Ryung Nam, and Woo Young Choi, "Logic-Compatible Charge-Trapping Tunnel Field Effect Transistors for Low-Power, High-Accuracy, and Large-Scale Neuromorphic Systems," Advanced Intelligent Systems, vol. 5, no. 11, p. 2300242, Nov. 2023. [SCI] DOI: 10.1002/aisy.202300242
[163] Jangsaeng Kim, Young-Tak Seo, Wonjun Shin, Woo Young Choi, Byung-Gook Park, and Jong-Ho Lee, "Hardware-Based Noisy Deep Q-Networks Using Low-Frequency Noise of Synaptic Devices for Efficient Exploration," IEEE Electron Device Letters, vol. 44, no. 9, pp. 1571-1574, Sep. 2023. [SCI] DOI: 10.1109/LED.2023.3301271
[162] Gyuweon Jung, Suyeon Ju, Kangwook Choi, Jaehyeon Kim, Seongbin Hong, Jinwoo Park, Wonjun Shin, Yujeong Jeong, Seungwu Han, Woo Young Choi, Jong-Ho Lee, "Reconfigurable Manipulation of Oxygen Content on Metal Oxide Surfaces and Applications to Gas Sensing," ACS Nano, vol. 17, no. 18, pp. 17790–17798, Aug. 2023 [SCI] DOI: 10.1021/acsnano.3c03034
[161] Gyuweon Jung, Jaehyeon Kim, Seongbin Hong, Hunhee Shin, Yujeong Jeong, Wonjun Shin, Dongseok Kwon, Woo Young Choi, Jong-Ho Lee, "Energy Efficient Artificial Olfactory System with Integrated Sensing and Computing Capabilities for Food Spoilage Detection," Advanced Science, p.2302506, Aug. 2023. [SCI] DOI:10.1002/advs.202302506
[160] Ho-Nam Yoo, Yeongheon Yang, Min-Kyu Park, Woo Young Choi, and Jong-Ho Lee, "Analysis of GIDL Erase Characteristics in Vertical NAND Flash Memory," Journal of Semiconductor Technology and Science, vol. 23, no. 3, pp. 196-201, Jun. 2023. [SCI] DOI:10.5573/JSTS.2023.23.3.196
[159] Siyoun Lee, Seong-Yeon Kim, Haesoon Oh, Jaesung Sim, and Woo Young Choi, "Influence of Hole Current Crowding on Snapback Breakdown in Multi-Finger MOSFETs," IEEE Access, vol. 11, pp. 60758-60762, Jun. 2023. [SCI] DOI:10.1109/ACCESS.2023.3285614
[158] Ji Ho Uhm, Jin Ho Chang, Joonggyu Kim, Eunmee Kwon, Woo Young Choi, "Azimuthal Charge Redistribution of Hemi-Cylindrical Vertical NAND Flash Memory," IEEE Electron Device Letters, vol. 44, no. 6, pp. 931-934, Jun. 2023. [SCI] DOI: 10.1109/LED.2023.3265986
[157] Ki Ryung Nam, Kwang Soo Kim*, and Woo Young Choi*, "Electrical Characterization by Counter-Doped Pocket Design in Tunnel FETs," IEEE Access, vol. 11, no. 4, pp. 30546-30554, Apr. 2023. [SCI] DOI: 10.1109/ACCESS.2023.3262285
[156] Dong-Oh Kim, Changha Kim, Hyun-Min Kim, Jonghyuk Park, Bosung Jeon, Daewoong Kwon, and Woo Young Choi, "Circular ferroelectric tunnel junctions for the improvement of memory window and endurance," Japanese Journal of Applied Physics, vol. 62, p. SG1044, Apr. 2023. [SCI] DOI: 10.35848/1347-4065/acc669
[155] Taejin Jang, Bosung Jeon, Seunghwan Song, and Woo Young Choi, "Diode-Connected Overpass Channel Synaptic Transistors for Extremely-Low-Power Neuromorphic Systems," IEEE Electron Device Letters, vol. 44, no. 5, pp. 833-836, May 2023. [SCI] DOI: 10.1109/LED.2023.3252579
[154] Yeon-Joon Choi, Suhyun Bang, Tae-Hyeon Kim, Kyungho Hong, Sungjoon Kim, Sungjun Kim, Byung-Gook Park, and Woo Young Choi, "Electric-Field-Induced Metal Filament Formation in Cobalt-Based CBRAM Observed by TEM," ACS Applied Electronic Materials, 5(3), pp. 1834-1843, Mar. 2023 [SCI] DOI: 10.1021/acsaelm.3c00034
[153] Jaehyeon Kim, Wonjun Shin, Seongbin Hong, Yujeong Jeong, Gyuweon Jung, Woo Young Choi, Jae-Joon Kim, Byung-Gook Park, and Jong-Ho Lee, "A novel pathway to construct gas concentration prediction model in real-world applications: Data augmentation; fast prediction; and interpolation and extrapolation," Sensors and Actuators B: Chemical, vol. 382, p. 133533, May 2023. [SCI] DOI: 10.1016/j.snb.2023.133533.
[152] Tae-Hyeon Kim, Kyungho Hong, Sungjoon Kim, Jinwoo Park, Sangwook Youn, Jong-Ho Lee, Byung-Gook Park, Hyungjin Kim*, and Woo Young Choi*, "Fuse Devices for Pruning in Memristive Neural Network," IEEE Electron Device Letters, vol. 44, no. 3, pp. 520-523, Mar. 2023. [SCI] DOI: 10.1109/LED.2023.3237651
[151] Jae Seung Woo, Jang Woo Lee, and Woo Young Choi, "Quantitative Hot Carrier Injection Analysis of N-Type Tunnel Field-Effect Transistors," IEEE Access, vol. 11, no. 2, pp. 14943-14950, Feb. 2023. [SCI] DOI: 10.1109/ACCESS.2023.3243578
[150] Young Suh Song, Sangwan Kim, Jang Hyun Kim, Garam Kim, Jong-Ho Lee, and Woo Young Choi, "Enhancement of Thermal Characteristics and On-Current in GAA MOSFET by Utilizing AlO-Based Dual-κ Spacer Structure," IEEE Transactions on Electron Devices, vol. 70, no. 1, pp. 343-348, Jan. 2023. [SCI] DOI: 10.1109/TED.2022.3223321
[149] Jong-Won Back, Ho-Nam Yoo, Jaehyeon Kim, Min-Kyu Park, Woo Young Choi, and Jong-Ho Lee, "String Current Compensation Method in VNAND Flash for Hardware-Based BNNs," IEEE Transactions on Electron Devices, vol. 69, no.12, pp. 6717-6721, Dec. 2022. [SCI] DOI: 10.1109/TED.2022.3216537
[148] Junmo Lee, Joon Hwang, Youngwoon Cho, Min-Kyu Park, Woo Young Choi, Sangbum Kim, and Jong-Ho Lee, "CRUS: A Hardware-Efficient Algorithm Mitigating Highly Nonlinear Weight Update in CIM Crossbar Arrays for Artificial Neural Networks," IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 8, no. 2, pp. 145-154, Dec. 2022. [SCI] DOI: 10.1109/JXCDC.2022.3220032
[147] Suhyun Bang, Sungjoon Kim, Kyungho Hong, Kannan Udaya Mohanan, Seongjae Cho*, and Woo Young Choi*, "Fabrication and characterization of silicon nano-tip memristor for low-power neuromorphic application," AIP Advances, vol. 12, no. 12, p.125217, Dec. 2022. [SCI] DOI: 10.1063/5.0117486
[146] Kyu-Ho Lee, Dongseok Kwon, Sung Yun Woo, Jong Hyun Ko, Woo Young Choi, Byung-Gook Park, and Jong-Ho Lee, "Highly Linear Analog Spike Processing Block Integrated With an AND-Type Flash Array and CMOS Neuron Circuits," IEEE Transactions on Electron Devices, vol. 69, no. 11, pp. 6065-6071, Nov. 2022. [SCI] DOI: 10.1109/TED.2022.3207707
[145] Jin Ho Chang, Ji Ho Uhm, Hyug Su Kwon, Eunmee Kwon, and Woo Young Choi, "Influence of Channel Hole Remaining Ratio on Hemi-Cylindrical Vertical NAND Flash Memory ," IEEE Electron Device Letters, vol. 43, no. 9, pp. 1432 - 1435, Sep. 2022. [SCI] DOI: 10.1109/LED.2022.3192545
[144] Jang Woo Lee, Jae Seung Woo, and Woo Young Choi, "Synaptic Tunnel Field-Effect Transistors for Extremely-Low-Power Operation," IEEE Electron Device Letters, vol. 43, no. 7, pp. 1149-1152, Jul. 2022. [SCI] DOI: 10.1109/LED.2022.3179173
[143] Hyug Su Kwon and Woo Young Choi, "Nanoelectromechanical (NEM) Devices for Logic and Memory Applications," Journal of Semiconductor Technology and Science, vol. 22, no. 3, pp. 188-197, Jun. 2022. [SCI] DOI:10.5573/JSTS.2022.22.3.188
[142] Hyunju Kim, Mannhee Cho, Sanghyun Lee, Hyug Su Kwon, Woo Young Choi, and Youngmin Kim, "Content-Addressable Memory System Using a Nanoelectromechanical Memory Switch," Electronics, vol. 11, no. 3, p. 481, Feb. 2022. [SCIE] DOI: 10.3390/electronics11030481
[141] Jisoo Yoon, Hyug Su Kwon, and Woo Young Choi, "Multi-Layer Nanoelectromechanical (NEM) Memory Switches for Multi-Path Routing," IEEE Electron Device Letters, vol. 43, no. 1, pp.162-165, Jan. 2022. [SCI] DOI: 10.1109/LED.2021.3130579
[140] Jae Seong Lee, Jisoo Yoon, and Woo Young Choi, "In-Memory Nearest Neighbor Search With Nanoelectromechanical Ternary Content-Addressable Memory," IEEE Electron Device Letters, vol. 43, no. 1, pp.154-157, Jan. 2022. [SCI] DOI: 10.1109/LED.2021.3131184
[139] Jang Woo Lee, Jae Seung Woo, and Woo Young Choi, "Tunneling Field-Effect Transistor for Neuromorphic Application," Journal of Semiconductor Engineering, vol. 2, no.3, 142-153, Dec. 2021. DOI:10.22895/jse.2021.0004
[138] Jae Seong Lee and Woo Young Choi, "Nanoelectromechanical-Switch-Based Ternary Content-Addressable Memory (NEMTCAM)," IEEE Transactions on Electron Devices, vol. 68, no. 10, pp.4903-4909, Oct. 2021. [SCI] DOI: 10.1109/TED.2021.3106886
[137] Kyung Min Koo, Woo Young Chung, Sang Yi Lee, Gyu Han Yoon, and Woo Young Choi, "Modeling of Statistical Variation Effects on DRAM Sense Amplifier Offset Voltage," Micromachines, vol. 12, p. 1145, Sep. 2021. [SCIE] DOI: 10.3390/mi12101145
[136] Jae Seong Lee and Woo Young Choi, "Nanoelectromechanical-Switch-Based Binary Content-Addressable Memory (NEMBCAM)," IEEE Access, vol. 9, pp. 70214-70220, May 2021. [SCI] DOI: 10.1109/ACCESS.2021.3078531
[135] Shinhee Kim, Jae Yeon Park, Seungwon Go, Hyug Su Kwon, Woo Young Choi, and Sangwan Kim, "A low-power nanoelectromechanical (NEM) device with Al-doped HfO2-based ferroelectric capacitor," Solid-State Electronics, vol. 175, p. 107956, Jan. 2021. [SCI] https://doi.org/10.1016/j.sse.2021.107956.
[134] Hye In Kim, Jung Min Sung, Hyung Uk Cho, Yong Jo Kim, Young Gwan Park, and Woo Young Choi, "LTPS TFTs with an Amorphous Silicon Buffer Layer and Source/Drain Extension," Electronics, vol. 10, no. 1, p. 29, Jan. 2021. [SCIE] DOI: 10.3390/electronics10010029
[133] Min Woo Kang and Woo Young Choi, "Investigation on the Hump Behavior of Gate-Normal Nanowire Tunnel Field-Effect Transistors (NWTFETs)," Applied Sciences, vol. 10, no. 24, p. 8880, Dec. 2020. [SCIE] DOI: 10.3390/app10248880
[132] Gwangryeol Baek, Jisoo Yoon, and Woo Young Choi, "Tri-state Nanoelectromechanical Memory Switches for the Implementation of a High-Impedance State," IEEE Access, vol. 8, no. 1, pp. 202006-202012, Nov. 2020. [SCI] DOI: 10.1109/ACCESS.2020.3036189
[131] Ji Wang Ko, Gwangryeol Baek, and Woo Young Choi, "Scaling Trends of Monolithic 3D Complementary Metal-Oxide-Semiconductor Nanoelectromechanical Reconfigurable Logic Circuits," IEEE Transactions on Electron Devices, vol. 67, no. 9, pp.3861-3867, Sep. 2020. [SCI] DOI: 10.1109/TED.2020.3008880
[130] Hyug Su Kwon, Ji Wang Ko and Woo Young Choi, "Island-Style Monolithic Three-Dimensional CMOS–NEM Reconfigurable Logic Circuits," IEEE Electron Device Letters, vol. 41, no. 8, pp. 1257-1260, Aug. 2020. [SCI] DOI: 10.1109/LED.2020.3001362
[129] Hyug Su Kwon and Woo Young Choi, "나노전기기계 스위치 및 메모리 기술," The Magazine of IEIE, vol.47, no.7, pp. 487-497, Jul. 2020.
[128] Min-Hee Kang, Hyun-Chan Jo, and Woo Young Choi, "Notched Anchor Design for Low Voltage Operation of Nanoelectromechanical (NEM) Memory Switches," Journal of Nanoscience and Nanotechnology, vol. 20, no. 7, pp. 4198-4202, Jul. 2020. [SCIE] DOI: 10.1166/jnn.2020.17789
[127] Ji Wang Ko and Woo Young Choi, "Monolithic-3D (M3D) Complementary Metal-Oxide-Semiconductor-Nanoelectromechanical (CMOS-NEM) Hybrid Reconfigurable Logic (RL) Circuits," Journal of Nanoscience and Nanotechnology, vol. 20, no. 7, pp. 4176-4181, Jul. 2020. [SCIE] DOI: 10.1166/jnn.2020.17790
[126] Woo Young Choi, "Negative Capacitance Vacuum Channel Transistors for Low Operating Voltage," Micromachines, vol. 11, no. 6, p.153, May 2020. [SCIE] DOI: 10.3390/mi11060543
[125] Faraz Najam, Sangwan Kim, Woo Young Choi, and Yun Seop Yu, "Physically Consistent Method for Calculating Trap-Assisted-Tunneling Current Applied to Line Tunneling Field-Effect-Transistor," IEEE Transactions on Electron Devices, vol. 67, no. 5, pp. 2106-2112, May 2020. [SCI] DOI: 10.1109/TED.2020.2982262
[124] Jang Woo Lee and Woo Young Choi, "Design Guidelines for Gate-Normal Hetero-Gate-Dielectric (GHG) Tunnel Field-Effect Transistors (TFETs)," IEEE Access, vol. 8, no. 1, pp. 67617-67624, Apr. 2020. [SCI] DOI: 10.1109/ACCESS.2020.2985125
[123] Min-Hee Kang and Woo Young Choi, "Dynamic Slingshot Operation for Low-Operation-Voltage Nanoelectromechanical (NEM) Memory Switches," IEEE Access, vol. 8, no. 1, pp. 65683-65688, Apr. 2020. [SCI] DOI: 10.1109/ACCESS.2020.2985105
[122] Jang Woo Lee and Woo Young Choi, "Design Guideline of Tunnel Field-Effect Transistors (TFETs) Considering Negative Differential Transconductance (NDT)," Solid State Electronics, vol. 163, p. 107659, Jan. 2020. [SCI]
[121] Tae Min Cha, Hyun Chan Jo, Hyug Su Kwon, and Woo Young Choi, "Active Region Formation of Nanoelectromechanical (NEM) Devices for CMOS-NEM Co-Integration," Journal of Nanoscience and Nanotechnology, vol. 19, no. 10, pp. 6123-6127, Oct. 2019. [SCIE]
[120] Hyun Chan Jo, Min Hee Kang, and Woo Young Choi, "Selection Line Optimization of Nanoelectromechanical (NEM) Memory Switches for Stress Relief," Journal of Semiconductor Technology and Science, vol. 19, no. 2, pp. 203-207, Apr. 2019. [SCIE]
[119] Seongun Shin, Gyuhan Yoon, and Woo Young Choi, "Influence of Etch Profiles on the Leakage Current and Capacitance of 3-D DRAM Storage Capacitors," Journal of Semiconductor Technology and Science, vol. 19, no. 2, pp. 208-213, Apr. 2019. [SCIE]
[118] Woo Young Choi, Gyuhan Yoon, Woo Young Chung, Younghoon Cho, Seongun Shin and Kwang Ho Ahn, "A Technology-Computer-Aided-Design-Based Reliability Prediction Model for DRAM Storage Capacitors," Micromachines, vol. 10, no. 4, p.256, Apr. 2019. [SCI]
[117] Woo Young Choi and Hyug Su Kwon, "Slingshot Pull-In Operation for Low-Voltage Nano-Electromechanical (NEM) Memory Switches," IEEE Transactions on Electron Devices, vol. 66, no. 4, pp. 2040-2043, Apr. 2019. [SCI]
[116] Ho Moon Lee, Hyun Chan Jo, Hyug Su Kwon, and Woo Young Choi, "Switching Voltage Analysis of Nanoelectromechanical (NEM) Memory Switches for Monolithic Three-Dimensional (M3D) CMOS-NEM Hybrid Reconfigurable Logic (RL) Circuits," IEEE Transactions on Electron Devices, vol. 65, no. 9, pp. 3780-3785, Sep. 2018. [SCI]
[115] Sangwan Kim and Woo Young Choi, "Compact Potential Model for Si1-xGex/Si Heterojunction Double-Gate Tunnel Field-Effect Transistors (TFETs)," Journal of Nanoscience and Nanotechnology, vol. 18, no.9, pp. 5953-5958, Sep. 2018. [SCIE]
[114] Hyun Chan Jo and Woo Young Choi, "Encapsulation of NEM Memory Switches for Monolithic-Three-Dimensional (M3D) CMOS-NEM Hybrid Circuits," Micromachines, vol. 9, no. 7, p.317, Jul. 2018. [SCI]
[113] Sangwan Kim, Woo Young Choi*, and Byung-Gook Park*, "Vertical-Structured Electron-Hole Bilayer Tunnel Field-Effect Transistor for Extremely-Low-Power Operation with High Scalability," IEEE Transactions on Electron Devices, vol. 65, no. 5, pp. 2010-2015, May 2018. [SCI] *co-corresponding authors
[112] Woo Young Choi, In Eui Lim, Heesauk Jhon, and Gyuhan Yoon, "On-Current Modeling of Sub-70-nm PMOSFETs Dependent on Hot-Carrier Stress Bias Conditions," Journal of Semiconductor Technology and Science, vol. 18, no. 2, pp. 131-138, Apr. 2018. [SCIE]
[111] Woo Young Choi, Hyuck-In Kwon, and Kwanyong Kim, "Lateral Nanoelectromechanical Relays for Reconfigurable Logic," Journal of Nanoelectronics and Optoelectronics, vol. 12, no. 12, pp. 1402-1405, Dec. 2017. [SCIE]
[110] Woo Young Choi, "Nanoelectromechanical Nonvolatile Memory Cells with Scaled Beam Dimensions," Journal of Nanoelectronics and Optoelectronics, vol. 12, no. 10, pp. 1134-1136, Oct. 2017. [SCIE]
[109] Hyug Su Kwon, Seung Kyu Kim, and Woo Young Choi, "Monolithic Three-Dimensional 65-nm CMOS-Nanoelectromechanical Reconfigurable Logic for Sub-1.2-V Operation," IEEE Electron Device Letters, vol. 38, no. 9, pp. 1317-1320, Sep. 2017. [SCI]
[108] In Huh, Sangchun Park, Mincheol Shin, and Woo Young Choi, "An Accurate Drain Current Model of Monolayer Transition-Metal Dichalcogenide Tunnel FETs ," IEEE Transactions on Electron Devices, vol. 64, no. 8, pp. 3502-3507, Aug. 2017. [SCI]
[107] Sangwan Kim and Woo Young Choi, "Improved compact model for double-gate tunnel field-effect transistors by the rigorous consideration of gate fringing field," Japanese Journal of Applied Physics, vol. 56, no. 8, pp. 084301, Jul. 2017. [SCI]
[106] Jang Woo Lee and Woo Young Choi, "Triple-Gate Tunnel FETs Encapsulated with an Epitaxial Layer for High Current Drivability," Journal of Semiconductor Technology and Science, vol. 17, no. 2, pp. 271-276, Apr. 2017. [SCIE]
[105] Ho Moon Lee and Woo Young Choi, "Mutually-Actuated-Nano-Electromechanical (MA-NEM) Memory Switches for Scalability Improvement," Journal of Semiconductor Technology and Science, vol. 17, no. 2, pp. 199-203, Apr. 2017. [SCIE]
[104] Seung Kyu Kim and Woo Young Choi, "Monolithic three-dimensional (M3D) tunnel FET (TFET) - nanoelectromechanical (NEM) hybrid reconfigurable logic circuits," Japanese Journal of Applied Physics, vol. 56, no. 4S, pp. 04CD12, Mar. 2017.[SCI]
[103] In Eui Lim, Heesauk Jhon, Gyuhan Yoon, and Woo Young Choi, "Drain-Current Modeling of Sub-70-nm PMOSFETs Dependent on Hot-Carrier Stress Bias Conditions," Journal of Semiconductor Technology and Science, vol. 17, no. 1, pp. 94-100, Feb. 2017. [SCIE]
[102] Woo Young Choi, "Influence of line-edge roughness (LER) on multiple-gate (MG) tunnel field-effect transistors (TFETs)," Japanese Journal of Applied Physics, vol. 56, no. 4S, pp. 04CD06, Feb. 2017. [SCI]
[101] Woo Young Choi, Hyug Su Kwon, Yong Jun Kim, Byungin Lee, Hyunseung Yoo, Sangmoo Choi, Gyu-Seog Cho, and Sung-Kye Park, "Influence of Intercell Trapped Charge (ITC) on Vertical NAND (VNAND) Flash Memory," IEEE Electron Device Letters, vol. 38, no. 2, pp. 164-167, Feb. 2017. [SCI]
[100] Woo Young Choi, "Effects of drain bias on the statistical variation of double-gate tunnel field-effect transistors," Japanese Journal of Applied Physics, vol. 56, no. 4S, pp. 04CD01, Jan. 2017. [SCI]
[99] Hee-Sauk Jhon, Jongwook Jeon, Myunggon Kang, and Woo Young Choi, "A sub-0.5 V operating RF-Low Noise Amplifier using tunneling-FET (TFET)," Japanese Journal of Applied Physics, vol. 56, no. 2, pp. 020303, Jan. 2017. [SCI]
[98] Woo Young Choi, Da Som Kim, Tae Ho Lee, Young Jun Kwon, Sung-Kun Park, and Gyuhan Yoon , "Influence of Electron and Hole Distribution on 2T SONOS Embedded NVM," Journal of Semiconductor Technology and Science, vol. 16, no. 5, pp. 624-629, Oct. 2016. [SCIE]
[97] Jang Woo Lee and Woo Young Choi, "Random Telegraph Noise Model of Tunnel Field-Effect Transistors," Journal of Nanoscience and Nanotechnology, vol. 16, no. 10, pp. 10264-10267, Oct. 2016. [SCIE]
[96] In Huh and Woo Young Choi, "Influence of the Source Doping Concentration on the Subthreshold Swing (SS) of Tunneling Field-Effect Transistors (TFETs)," Journal of Nanoscience and Nanotechnology, vol. 16, no. 10, pp. 10241-10246, Oct. 2016. [SCIE]
[95] Jong Han Park and Woo Young Choi, "Esaki-Tunneling-Assisted Tunnel Field-Effect Transistors for Sub-0.7-V Operation," Journal of Nanoscience and Nanotechnology, vol. 16, no. 10, pp. 10237-10240, Oct. 2016. [SCIE]
[94] Sang Wan Kim and Woo Young Choi, "Hump Effects of Germanium / Silicon Heterojunction Tunnel Field-Effect Transistors," IEEE Transactions on Electron Devices, vol. 63, no. 6, pp. 2583-2588, Jun. 2016. [SCI]
[93] Woo Young Choi and Hyun Kook Lee, "Demonstration of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors (HG TFETs)," Nano Convergence, vol. 3, no. 1, pp. 1-15, Jun. 2016.
[92] Woo Young Choi, Jae Hwan Han, and Tae Min Cha, “Multi-Bit Nano-Electromechanical Nonvolatile Memory Cells (Zigzag T Cells) for the Suppression of Bit-to-Bit Interference," Journal of Nanoscience and Nanotechnology, vol. 16, no. 5, pp. 5164-5167, May 2016. [SCI]
[91] Kyoung Min Choi, Seung Kyu Kim, and Woo Young Choi, “Influence of Number Fluctuation and Position Variation of Channel Dopants and Gate Metal Grains on Tunneling Field-Effect Transistors (TFETs)," Journal of Nanoscience and Nanotechnology, vol. 16, no. 5, pp. 5255-5258, May 2016. [SCI]
[90] In Huh, Woo Young Cheon, and Woo Young Choi, "Subthreshold-swing-adjustable tunneling-field-effect-transistor-based random-access memory for nonvolatile operation," Applied Physics Letters , vol. 108, p.153506, Apr. 2016. [SCI]
[89] Woo Young Choi, "Miller effect suppression of tunnel field-effect transistors (TFETs) using capacitor neutralization," IET Electronics Letters, vol. 52, no. 8, pp. 659-661, Apr. 2016. [SCI]
[88] Sang Wan Kim, Jang Hyun Kim, Tsu-Jae King Liu, Woo Young Choi, and Byung-Gook Park, "Demonstration of L-Shaped Tunnel Field-Effect Transistors," IEEE Transactions on Electron Devices, vol. 63, no. 4, pp. 1774-1778, Apr. 2016. [SCI]
[87] Seung Kyu Kim and Woo Young Choi, “Impact of gate dielectric constant variation on tunnel field-effect transistors (TFETs)," Solid-State Electronics, vol. 116, no. 2, pp. 88-94, Feb. 2016. [SCI]
[86] Jong Han Park and Woo Young Choi, "IoT용 초저전력 터널링 트랜지스터 소자 기술," The Magazine of IEIE, vol.43, no.1, pp. 18-23, Jan. 2016.
[85] Songnam Lim, Jong-Ho Lee, Woo Young Choi, and Il Hwan Cho, "Pull-In Voltage Modeling of Graphene Formed Nickel Nano Electro Mechanical Systems (NEMS)," Journal of Semiconductor Technology and Science, vol. 15, no. 6, pp. 647-652, Dec. 2015. [SCIE]
[84] Woo Young Choi, “Design Guidelines of Tunneling Field-Effect Transistors for the Suppression of Work-Function Variation," IET Electronics Letters, vol. 51, no. 22, pp. 1819-1821, Nov. 2015. [SCI]
[83] Woo Young Choi and Yong Jun Kim, “Three-Dimensional Integration of Complementary Metal-Oxide-Semiconductor (CMOS)-Nano-Electromechanical (NEM) Hybrid Reconfigurable Circuits," IEEE Electron Device Letters, vol. 36, no. 9, pp. 887-889, Sep. 2015. [SCI]
[82] Song Hun Choi and Woo Young Choi, "차세대 저전력 터널링 트랜지스터," The Magazine of IEIE, vol.42, no.7, pp. 630-635, Jul. 2015.
[81] Jaesung Jo, Woo Young Choi, Jung-Dong Park, Jae Won Shim, Hyun-Yong Yu, and Changhwan Shin, “Negative Capacitance in Organic/Ferroelectric Capacitor to Implement Steep Switching MOS Devices," Nano Letters, vol. 15, no. 7, pp. 4553-4556, Jul. 2015. [SCI]
[80] Kyoung Min Choi, Wonsok Lee, Keun-Ho Lee, Young-Kwan Park, and Woo Young Choi, “Influence of Preferred Gate Metal Grain Orientation on Tunneling Field-Effect Transistors (TFETs)," IEEE Transactions on Electron Devices, vol. 62, no. 4, pp. 1353-1356, Apr. 2015. [SCI]
[79] Woo Jin Jeong, Tae Kyun Kim, Jung Min Moon, Min Gyu Park, Young Gwang Yoon, Byeong Woon Hwang, Woo Young Choi, Mincheol Shin, and Seok-Hee Lee, “Germanium Electron-Hole Bilayer Tunnel Field-Effect Transistors with a Symmetrically Arranged Double Gate," Semiconductor Science and Technology, vol. 30, no. 3, pp. 035021, Mar. 2015. [SCI]
[78] Eui-Young Song, Jaebum Cho, Hwi Kim, Woo Young Choi, and Byoungho Lee, “Double bi-material contilever structures for complex surface plasmon modulation," Optics Express, vol. 23, no. 5, pp. 5500-5507, Mar. 2015. [SCI]
[77] Yong Jun Kim and Woo Young Choi, “Nonvolatile Nano-Electromechanical (NEM) Memory Switches for Low-Power and High-Speed Field-Programmable Gate Arrays (FPGAs)," IEEE Transactions on Electron Devices, vol. 62, no. 2, pp. 673-679, Feb. 2015. [SCI]
[76] Byeong-In Choe, Jung-Kyu Lee, Bora Lee, Kwanyong Kim, Woo Young Choi, Byung Hee Hong, and Jong-Ho Lee, “Fabrication and Electrical Characterization of Graphene Formed Chemically on Nickel Nano Electro Mechanical System (NEMS) Switch," Journal of Nanoscience and Nanotechnology, vol. 14, no. 12, pp.9418-9424, Dec. 2014. [SCI]
[75] Jae Hwan Han, Jiyong Song, and Woo Young Choi, “Scale effects on stiction-induced release voltage shift of nano-electromechanical (NEM) memory cells," Journal of Nanoscience and Nanotechnology, vol. 14, no. 12, pp.9589-9593, Dec. 2014. [SCI]
[74] Boram Han, Ji Yong Song, and Woo Young Choi, “ Influence of Fringe Field on Nano-Electromechanical (NEM) Memory Cells,” IEEE Transactions on Nanotechnology, vol. 13, no. 6, pp.1102-1106, Nov. 2014. [SCI]
[73] Boram Han and Woo Young Choi, "Fringe Field Effects on Transient Characteristics of Nano-Electromechanical (NEM) Nonvolatile Memory Cells," Journal of Semiconductor Technology and Science, vol. 14, no. 5, pp. 609-614, Oct. 2014. [SCIE]
[72] Jae Hwan Han, Hyunjin Lee, Wansoo Kim, Gyuhan Yoon, and Woo Young Choi, "On-State Resistance Instability of Programmed Antifuse Cells during Read Operation," Journal of Semiconductor Technology and Science, vol. 14, no. 5, pp. 503-507, Oct. 2014. [SCIE]
[71] Ning Xi, Eou-Sik Cho, Woo Young Choi, and Il Hwan Cho, “ Disturbance characteristics of charge trap flash memory with tunneling field effect transistor,” Japanese Journal of Applied Physics, vol. 53, pp. 114201, Oct. 2014. [SCI]
[70] Jae Hwan Han, Kwanyong Kim, and Woo Young Choi, “Bit-to-Bit Interference of Multi-Bit Nano-Electromechanical Memory Cells (T Cells),” IEEE Transactions on Nanotechnology, vol. 13, no. 4, pp. 659-666, Jul. 2014. [SCI]
[69] Kwanyong Kim, Kwangseok Lee, Keun-Ho Lee, Young-Kwan Park, and Woo Young Choi, "A Finite Element Model for Bipolar Resistive Random Access Memory," Journal of Semiconductor Technology and Science, vol. 14, no. 3, pp. 268-273, Jun. 2014. [SCIE]
[68] Yong Jun Kim, Jun Geun Kang, Byungin Lee, Gyu-Seog Cho, Sung-Kye Park, and Woo Young Choi, “ Effects of Abnormal Cell-to-Cell Interference on NAND Flash Memory,” Japanese Journal of Applied Physics, vol. 53, no. 4S, pp. 04ED12, Mar. 2014. [SCI]
[67] Kwanyong Kim, Seong Jun Yoon and Woo Young Choi, “ Dual Random Circuit Breaker Network Model with Equivalent Thermal Circuit Network,” Applied Physics Express, Vol. 7, No. 2, pp. 024203-1- 024203-4, Feb. 2014. [SCI]
[66] Hyun Kook Lee and Woo Young Choi, "Linearity of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors," Journal of Semiconductor Technology and Science, vol. 13, no. 6, pp. 551–555, Dec. 2013. [SCIE]
[65] Chun Woong Park, Woo Young Choi, Jong Ho Lee, and Il Hwan Cho, "Reduction of ambipolar characteristics of vertical channel tunneling field effect transistor by using dielectric sidewall ," Semiconductor Science and Technology. vol. 28, no. 11, pp. 115022, Nov. 2013. [SCI]
[64] Eui-Young Song, Hwi Kim, Woo Young Choi, and Byoungho Lee, "Active directional beaming by mechanical actuation of double-sided plasmonic surface gratings ," Optics Letters , Vol. 38, no. 19, pp. 3827–3829, Oct. 2013. [SCI]
[63] Sang Wan Kim, Woo Young Choi, Min-Chul Sun, and Byung-Gook Park, "Investigation on the Corner Effect of L-shaped Tunneling Field-Effect Transistors and Their Fabrication Method," Journal of Nanoscience and Nanotechnology, vol. 13, no. 9, pp. 6376-6381, Sep. 2013. [SCI]
[62] Byung Kyu Park, Woo Young Choi, Eou Sik Cho, and Il Hwan Cho, "Development of sacrificial layer wet etch process of TiNi for nano-electro-mechanical device application,"Journal of Semiconductor Technology and Science, vol. 13, no. 4, pp. 410-414, Aug. 2013. [SCIE]
[61] Kyoung Min Choi and Woo Young Choi, "Work-Function Variation Effects of Tunneling Field-Effect Transistors (TFETs)," IEEE Electron Device Letters,vol. 34, no. 8, pp. 942-944, Aug. 2013. [SCI]
[60] Sang Wan Kim, Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park, "L-shaped Tunneling Field-Effect Transistors for Complementary Logic Applications," IEICE Transactions on Electronics, vol. E96-C, no. 5, pp. 634-638, May 2013. [SCIE]2
[59] Woo Young Choi, Min Su Han, Boram Han, Dongsun Seo, and Il Hwan Cho, "Modeling of Triangular Sacrificial Layer Residue Effect in Nano-Electro-Mechanical Nonvolatile Memory," IEICE Transactions on Electronics, vol. E96-C, no. 5, pp. 714-717, May 2013. [SCIE]
[58] Gibong Lee, Jung-Shik Jang, and Woo Young Choi, "Dual-Dielectric-Constant Spacer Hetero-Gate-Dielectric Tunneling Field-Effect Transistors," Semiconductor Science and Technology, vol. 28, pp. 052001, Apr. 2013. [SCI]
[57] Jung-Shik Jang, Hyun Kook Lee, and Woo Young Choi, "Random Dopant Fluctuation Effects of Tunneling Field-Effect Transistors (TFETs)," Journal of the Institute of Electronics Engineers of Korea, vol. 49, no. 12, pp. 179-183, Dec. 2012.
[56] Woo Young Choi, "Development of a Nano-Electro-Mechanical Memory Simulator," Journal of the Institute of Electronics Engineers of Korea, vol. 49, no. 10, pp. 122-127, Oct. 2012.
[55] Min Jin Lee and Woo Young Choi, "'Effects of Device Geometry on Hetero-Gate-Dielectric Tunneling Field-Effect Transistors (HG TFETs)," IEEE Electron Device Letters, vol. 33, no.10, pp 1459-1461, Oct. 2012. [SCI]
[54] Sang Wan Kim, Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, and Byung-Gook Park, "Design guideline of Si-Based L-Shaped Tunneling Field-Effect Transistors," Japanese Journal of Applied Physics, vol. 51, no. 6, pp. 06FE09-1-06FE03-4, Jun. 2012. [SCI]
[53] Jae Sung Lee, Woo Young Choi, and In Man Kang, "Characteristics of Gate-All-Around Hetero-Gate-Dielectric Tunneling Field-Effect Transistors," Japanese Journal of Applied Physics, vol. 51, no. 6, pp. 06FE03-1-06FE03-5, Jun. 2012. [SCI]
[52] Gibong Lee and Woo Young Choi, "Low-Power Circuit Applicability of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors (HG TFETs)," IEICE Transactions on Electronics, vol. E95-C, no. 5, pp.910-913, May 2012. [SCIE]
[51] Boram Han and Woo Young Choi, "Analytical Model of Nano-Electromechanical (NEM) Nonvolatile Memory Cells," IEICE Transactions on Electronics, vol. E95-C, no. 5, pp.914-916, May 2012. [SCIE]
[50] Kwangseok Lee and Woo Young Choi, "Multibit Operation of Nanoelectromechanical Memory Cells," IEEE Electron Device Letters,vol. 33, no.3, pp 309-311, Mar. 2012. [SCI]
[49] Kwangseok Lee, Jung-Shik Jang, Yongwoo Kwon, Keun-Ho Lee, Young-Kwan Park, and Woo Young Choi, "A Unified Model for Unipolar Resistive Random Access Memory," Applied Physics Letters, vol. 100, no. 8, pp. 083509, Mar. 2012. [SCI]
[48] Min Jin Lee and Woo Young Choi, “Dependency of Tunneling Field-Effect Transistor (TFET) Characteristics on Operation Regions,” Journal of Semiconductor Technology and Science, vol. 11, no. 4, pp. 287-294, Dec. 2011. [SCIE]
[47] Jung-Shik Jang and Woo Young Choi, "Ambipolarity Factor of Tunneling Field-Effect Transistors (TFETs)," Journal of Semiconductor Technology and Science, vol. 11, no. 4, pp. 272-277, Dec. 2011. [SCIE]
[46] In Man Kang, Jung-Shik Jang, and Woo Young Choi, "Radio Frequency Performance of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors," Japanese Journal of Applied Physics, vol. 50, no. 12, pp. 124301-1-124301-4, Dec. 2011. [SCI]
[45] Woojun Lee and Woo Young Choi, "Influence of Inversion Layer on Tunneling Field-Effect Transistors," IEEE Electron Device Letters, vol. 32, no.9, pp 1191-1193, Sep. 2011. [SCI]
[44] Min Jin Lee and Woo Young Choi, “Distribution of post-breakdown resistance of MOSFETs," IEICE Electronics Express, vol.8, no.16, pp. 1309-1314, Sep. 2011. [SCIE]
[43] Min Jin Lee and Woo Young Choi, "Analytical Model of Single-Gate Silicon-on-Insulator (SOI) Tunneling Field-Effect Transistors (TFETs)," Solid-State Electronics, vol. 63, issue 1, pp. 110-114, Sep. 2011.[SCI]
[42] Woojun Lee and Woo Young Choi, "A Novel Capacitorless 1T DRAM Cell for Data Retention Time Improvement," IEEE Transactions on Nanotechnology, vol. 10, no. 3, pp. 462-466, May 2011. [SCI]
[41] Seung Hyeun Roh, Kwangsoo Kim, and Woo Young Choi, "Scaling Trend of Nano-Electro-Mechanical (NEM) Nonvolatile Memory Cells Based on Finite Element Analysis (FEA)," IEEE Transactions on Nanotechnology, vol. 10, no. 3, pp. 647-651, May 2011. [SCI]
[40] Kwangseok Lee and Woo Young Choi, "Nanoelectromechanical Memory Cell (T Cell) for Low-Cost Embedded Nonvolatile Memory Applications", IEEE Transactions on Electron Devices, vol.58, no.4, pp. 1264-1267, Apr. 2011. [SCI]
[39] Woojun Lee, Kwangsoo Kim, and Woo Young Choi, "Novel 1T DRAM Cell for Low-Voltage Operation and Long Data Retention Time," IEICE Transactions on Electronics, vol. E94-C, no. 1, pp. 110-115, Jan. 2011. [SCIE]
[38] Woo Young Choi and Woojun Lee, "Hetero-Gate-Dielectric Tunneling Field-Effect Transistors," IEEE Transactions on Electron Devices, vol. 57, no. 9, pp. 2317-2319, Sep. 2010. [SCI]
[37] Woo Young Choi, "Characterization of surface forces for electro-mechanical memory cells," IEICE Electronics Express, vol. 7, no. 12, pp. 827-831, Jul. 2010. [SCI]
[36] Woo Young Choi, "Comparative Study of Tunneling Field-Effect Transistors and Metal–Oxide–Semiconductor Field-Effect Transistors," Japanese Journal of Applied Physics, vol. 49, no. 4, pp. 04DJ12-1-04DJ12-3, Apr. 2010. [SCI]
[35] Woojun Lee and Woo Young Choi, "Quantitative Analysis of Hump Effects of Gate-All-Around Metal–Oxide–Semiconductor Field-Effect Transistors," Japanese Journal of Applied Physics, vol. 49, no. 4, pp. 04DC11-1-04DC11-3, Apr. 2010. [SCI]
[34] Woo Young Choi, "Applications of impact-ionization metal-oxide-semiconductor (I-MOS) devices to circuit design," Current Applied Physics, vol. 10, no. 2, pp. 444-451, Mar. 2010. [SCI]
[33] Woo Young Choi, "Design and Scaling of Nano-Electro-Mechanical Non-Volatile Memory (NEMory) Cells," Current Applied Physics, vol. 10, no. 1, pp. 311-316, Jan. 2010. [SCI]
[32] Woo Young Choi, "Three-Dimensional Stackable Electromechanical Nonvolatile Memory Cell (H Cell) for Four-Bit Operation," IEEE Electron Device Letters, vol. 31, no. 1, pp. 29-31, Jan. 2010. [SCI]
[31] Woo Young Choi, "A new method for stable numerical differentiation," Current Applied Physics, vol. 9, no. 6, pp. 1463-1466, Nov. 2009. [SCI]
[30] Jong Pil Kim, Jae Young Song, Sang Wan Kim, Jae Hyun Park, Woo Young Choi, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park, “Self-Aligned Asymmetric Metal-Oxide-Semiconductor Field Effect Transistors Fabricated on Silicon-on-Insulator,” Japanese Journal of Applied Physics, vol. 48, no. 9, pp. 091201, Sep., 2009. [SCI]
[29] Woo Young Choi, "Effect of Device Parameters on the Breakdown Voltage of Impact-Ionization Metal–Oxide–Semiconductor Devices," Japanese Journal of Applied Physics, vol. 48, no. 4, pp. 040203-1-040203-3, Apr. 2009. [SCI]
[28] Woo Young Choi and Tsu-Jae King Liu, "Reliability of Nanoelectromechanical Nonvolatile Memory (NEMory) Cells," IEEE Electron Device Letters, vol. 30, no. 3, pp. 269-271, Mar. 2009. [SCI]
[27] Woo Young Choi, Taro Osabe, and Tsu-Jae King Liu, "Nano-Electro-Mechanical Nonvolatile Memory (NEMory) Cell Design and Scaling," IEEE Transactions on Electron Devices, vol. 55, no. 12, pp. 3482-3488, Dec. 2008. [SCI]
[26] Jong Pil Kim, Woo Young Choi, Jae Young Song, Sang Wan Kim, Jong Duk Lee, and Byung-Gook Park, "Design and Fabrication of Asymmetric MOSFETs Using a Novel Self-Aligned Structure," IEEE Transactions on Electron Devices, vol. 54, no. 11, pp. 2969-2974, Nov. 2007. [SCI]
[25] Woo Young Choi, Byung-Gook Park, Jong Duk Lee and Tsu-Jae King Liu, "Tunneling Field-Effect Transistors (TFETs) with Subthreshold Swing (SS) Less Than 60 mV/dec," IEEE Electron Device Letters, vol. 28, no. 8, pp. 743-745, Aug. 2007. [SCI]
[24] Jong Pil Kim, Woo Young Choi, Jae Young Song, Seongjae Cho, Sang Wan Kim, Jong Duk Lee, and Byung-Gook Park, “Design and Simulation of Asymmetric MOSFETs”, IEICE Trans. Electron., vol. E90-C, pp. 978-982, May 2007. [SCI]
[23] Hoon Jeong, Yeun Seung Lee, Sangwoo Kang, Il Han Park, Woo Young Choi, Hyungcheol Shin, Jong Duk Lee, and Byung-Gook Park, "Capacitorless Dynamic Random Access Memory Cell with Highly Scalable Surrounding Gate Strcucture," Japanese Journal of Applied Physics, vol. 46, no. 4B, pp. 2143-2147, Apr. 2007. [SCI]
[22] Jae Young Song, Woo Young Choi, Jong Pil Kim, Sang Wan Kim, Jong Duk Lee, and Byung-Gook Park, "Novel Gate-All-Around Metal-Oxide-Semicondurctor Field Effect Transistors with Self-Aligned Structure", Japanese Journal of Applied Physics, vol. 46, no. 4B, pp. 2046-2049, Apr. 2007. [SCI]
[21] Woo Young Choi, Jong Duk Lee, and Byung-Gook Park, "Novel Tunneling Devices with Multi-Functionality," Japanese Journal of Applied Physics, vol. 46, no. 4B, pp. 2622-2625, Apr. 2007. [SCI]
[20] Woo Young Choi, Jong Duk Lee, and Byung-Gook Park, “Integration Process of Impact-Ionization Metal-Oxide-Semiconductor Devices with Tunneling Field-Effect-Transistors and Metal-Oxide-Semiconductor Field-Effect Transistors," Japanese Journal of Applied Physics, vol. 46, no. 1, pp. 122~124, Jan. 2007. [SCI]
[19] Woo Young Choi, Byung Yong Choi, Dong-Won Kim, Choong-Ho Lee, Donggun Park, Jong Duk Lee, and Byung-Gook Park, "25-nm Programmable Virtual Source/Drain MOSFETs Using a Twin SONOS Memory Structure," Solid-State Electronics, vol. 50, issue 6, pp. 914-919, Jun. 2006. [SCI]
[18] Jae Young Song, Woo Young Choi, Ju Hee Park, Jong Duk Lee, and Byung-Gook Park, "Design Optimization of Gate-All-Around (GAA) MOSFETs," IEEE Transactions on Nanotechnology, vol. 5, no. 3, pp. 186-191, May 2006. [SCIE]
[17] Woo Young Choi, Jae Young Song, Jong Duk Lee, and Byung-Gook Park, "Effect of Source Extension Junction Depth and Substrate Doping Concentration on I-MOS Device Characteristics," IEEE Transactions on Electron Devices, vol. 53, no. 5, pp. 1282-1285, May 2006. [SCI]
[16] Woo Young Choi, Jong Duk Lee, and Byung-Gook Park, "Characterization and Design Consideration of 80-nm Self-Aligned N-/P-Channel I-MOS Devices," Journal of Semiconductor Technology and Science, vol. 6, no. 1, pp. 43-51, Mar. 2006.
[15] Byung-Gook Park, Byung Yong Choi, Woo Young Choi, Yong Kyu Lee, Jong Duk Lee, Hyungcheol Shin, Suk-Kang Sung, Tae-Yong Kim, Eun Suk Cho, Byung Kyu Cho, Keun Hee Bai, Dong-Dae Kim, Dong-Won Kim, Choong-Ho Lee and Donggun Park, "Highly Manufacturable and Reliable 80-nm Gate Twin Silicon-Oxide-Nitride-Oxide-Silicon Memory Transistor," Jpn. J. Appl. Phys. vol. 44, pp. L 1214-L 1217, no. 39, Sep. 2005. [SCI]
[14] Woo Young Choi, Jae Young Song, Jong Duk Lee, Young June Park, and Byung-Gook Park, "A Novel Biasing Scheme for I-MOS (Impact-Ionization MOS) Devices," IEEE Transactions on Nanotechnology, vol. 4, no. 3, pp. 322-325, May 2005. [SCIE]
[13] Woo Young Choi, Jae Young Song, Jong Duk Lee, Young June Park, and Byung-Gook Park, "100nm N-/P-Channel I-MOS Using a Novel Self-Aligned Structure " IEEE Electron Device Letters, vol. 26, no. 4, pp. 261-263, Apr. 2005. [SCI]
[12] Woo Young Choi, Hwi Kim, Byoungho Lee, Jong Duk Lee, and Byung-Gook Park, "Stable Threshold Voltage Extraction Using Tikhonov’s Regularization Theory" IEEE Transactions on Electron Devices, vol. 51, no. 11, pp. 1833-1839, Nov. 2004. [SCI]
[11] Woo Young Choi, Dong Soo Woo, Byung Yong Choi, Jong Duk Lee and Byung-Gook Park, "Stable Extraction of Threshold Voltage Using Transconductance Change Method for CMOS Modeling, Simulation and Characterization," Jpn. J. Appl. Phys. vol. 43, pp. 1759-1762, Part 1, no. 4B, Apr. 2004. [SCI]
[10] Woo Young Choi, Byung Yong Choi, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "Stable Extraction of Linearity (VIP3) for Nanoscale RF CMOS Devices," IEEE Microwave and Wireless Components Letters, vol. 14, issue 2, pp. 83-85, Feb. 2004. [SCI]
[9] Woo Young Choi, Byung Yong Choi, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "Reverse-Order Source/Drain with Double Offset Spacer Design Optimization for Sub-50-nm Low-Power MOSFETs," Journal of Korean Physical Society, vol. 44, no. 1, pp. 60-64, Jan. 2004. [SCI]
[8] Woo Young Choi, Byung Yong Choi, Dong-Soo Woo, Jong Duk Lee, and Byung-Gook Park, "Reverse-Order Source/Drain Formation with Double Offset Spacer (RODOS) for Low-Power and High-Speed Application," IEEE Trans. on Nanotechnology, vol. 2, issue 4, pp. 210-216, Dec. 2003. [SCI]
[7] Dong-Soo Woo, Byung Yong Choi, Woo Young Choi, Myeong Won Lee, Jong Duk Lee, and Byung-Gook Park, "30 nm self-aligned finfet with large source/drain fan-out structure," IEE Electronics Letters, vol. 39, issue. 15, pp. 1154~1155, Jul. 2003. [SCI]
[6] Kyung-Hoon Chung, Woo Young Choi, Suk-Kang Sung, Dae Hwan Kim, Jong Duk Lee, and Byung-Gook Park, "Pattern multiplication method and the uniformity of nanoscale multiple lines," J. Vac. Sci. Technol. B. vol. 21, issues 4, pp. 1491-1495, July 2003. [SCI]
[5] Dong-Soo Woo, Jong-Ho Lee, Woo Young Choi, Byung-Yong Choi, Young-Jin Choi, Jong Duk Lee, and Byung-Gook Park, "Electrical Characteristics of FinFET With Vertically Nonuniform Source/Drain Doping Profile," IEEE Trans. on Nanotechnology, vol. 1, no. 4, pp. 233-237, Dec. 2002. [SCIE]
[4] Woo Young Choi, Byung Yong Choi, Young Jin Choi, Dong-Soo Woo, Suk-Kang Sung, Jong Duk Lee and Byung-Gook Park, "Fabrication of a 30-nm Planar nMOSFETs Based on the Sidewall Patterning Technique," Journal of The Korean Physical Society, vol. 41, no. 4, pp. 497-500, Oct. 2002. [SCI]
[3] Kyung-Hoon Chung, Suk-Kang Sung, Dae Hwan Kim, Woo Young Choi, Cheon An Lee, Jong Duk Lee and Byung-Gook Park, "Nanoscale Multi-Line Patterning Using Sidewall Structure," Jpn. J. Appl. Phys. vol. 41, pp. 4410-4414, part 1, no. 6B, Jun. 2002. [SCI]
[2] Byung Yong Choi, Woo Young Choi, Jong Duk Lee, and Byung-Gook Park, "50nm MOSFETs with side-gates for induced source/drain extension," IEE Electronics Letters, vol. 38, no. 11, pp. 526~527, May 2002. [SCI]
[1] Woo Young Choi, Byung Yong Choi, Dong Soo Woo, Young Jin Choi, Jong Duk Lee, and Byung-Gook Park, "Side-Gate Design Optimization of 50 nm MOSFETs with Electrically Induced Source/Drain," Jpn. J. Appl. Phys. vol. 41, part 1, no. 4B, pp. 2345-2347, Apr. 2002. [SCI]