I am a Postdoctoral Researcher at the Intelligent Circuits, Architectures, and Systems (iCAS) Laboratory within the SJTU Global College (SJTU-GC) of Shanghai Jiao Tong University. My academic journey includes a Ph.D. in Electrical Engineering from Shiv Nadar University, where I conducted research under the guidance of Prof. Sonal Singhal in the Microelectronics Laboratory, focusing on reliability-aware brain-inspired circuits and systems. I hold an M.Tech in Electronics and Communication Engineering from the National Institute of Technology (NIT) Hamirpur and a B.Tech from Vasireddy Venkatadri Institute of Technology (VVIT), Guntur.

Prior to my post-doctoral, I gained valuable industry experience at Cyient Limited, initially as an ASIC Design Engineer specializing in analog circuit design for precision applications, and subsequently as an AMS Verification Engineer. In these roles, I developed SystemVerilog (SV) verification environments for mixed-signal designs and contributed to critical projects including the receiver path of High Bandwidth Memory (HBM) systems and power management integrated circuit (PMIC) blocks.

My research expertise spans neuromorphic computing, SRAM-based In-Memory Computing architectures, CMOS circuit reliability analysis, and emerging memory devices. Through this interdisciplinary work, I have established a strong publication record with multiple peer-reviewed articles in SCI-indexed journals and conference proceedings. My current research aims to address fundamental challenges in next-generation computing and memory technologies, with applications spanning artificial intelligence accelerators, advanced driver-assistance systems (ADAS), and energy-efficient computing paradigms.