Best oral presentation in the session and awarded travel grant in iSES-2018 conference
Research Fellowship from Shiv Nadar University, India
Teaching Assistantship from MHRD, India—NIT Hamirpur
Qualified GATE Entrance Test in 2013, 2014, 2015
Won prizes in technical quizzes at various college festivals.
Won second prize at project-expo, VIVA VVIT 2012
"Grand Challenge: LLM-Based Analog Circuit Design Competition", organized by IEEE AICAS Grand Challenge team
"Short Course in Modeling and Simulation of Nano Transistors," organized by Nanolab @IIT Kanpur
Participated in the workshop to learn different aspects of nanotransistors, such as compact modeling, TCADsimulations, and electrical characterization
Trained in different Electronic Design Automation (EDA) tools
"Tutorial Session in Neuromorphic Devices," organized by ICEE 2020 at IIT Delhi
Participated in a tutorial session on the importance of neuromorphic computing in today’s world and how emerging devices are part of next-generation computing
"Physical Design and Verification Internship Program," organized by Entuple Technologies Pvt. Ltd.
Executed the RTL and Physical Synthesis flow of UART using Cadence Genus
Carried out static timing analysis (STA) using the Cadence Tempus tool
Performed physical design analysis for the I2C netlist using the Cadence Innovus tool
Completed internship and earned a STAR certificate for achieving a good grade in quizzes and assignments
"Indian Nanoelectronics User Program (INUP) Workshop," organized by Centre for Nanoscience and Engineering (CeNSE)-IISC Bangalore, March 2015
"ARM university competition," organized by the National Institute of Technology-Hamirpur.