As a postdoctoral researcher, I'm currently pursuing exciting opportunities in a number of cities. Please go through my educational or professional background, experiences, or passions. 

Doctor of Philosophy (Ph. D.)

Electrical Engineering Dept., 

Shiv Nadar University, NCR-Delhi

01/01/2017 - 28/05/2022

Ph. D. Advisor: Dr. Sonal Singhal

Ph.D. Thesis Title: "Design and Analysis of Reliability-aware CMOS circuits for a Neuromorphic System"

• Investigated the impact of BTI along process variability on SRAM and its peripheral circuits 

• Examined the impact of different NBTI variability distributions on FinFET-based SRAM cell

• Design and implement various neuromorphic circuits 

  1. Silicon Neurons (Axon-Hillock, Simplified-LIF, Voltage-LIF, Differential Pair Integrator-LIF)

  2. Silicon Synapse (Linear charge Discharge, Log-Domain Integrator, Differential Pair Integrator)

• Proposed Reliability-Aware & Energy-Efficient Silicon Neurons (AH, SLIF)

• Proposed and implemented Reliability-Aware & low-power Temporal Neuromorphic Encoder

• Proposed novel Reliability-Aware & energy-efficient neuromorphic system (SLIFMEM)

• Design and Implement 4X4 memristor-based crossbar architecture

Masters in Technology (M. Tech)

Electronics and Communications Engineering Dept., 

National Institute of Technology (NIT), Hamirpur

15/07/2014 - 31/07/2016

M.Tech Advisor: Dr. Phenomon Daniel 

M.Tech dissertation titled "Analysis and Implementation of Image Processing Filters on FPGA" 

• Reviewed various image processing filters using Matlab for autonomous driver assistance system

• Generated HDL code for image processing filters using Matlab HDL coder and Vivado HLS tools

• Created IPs of these filters and executed them on ZYBO to analyze their performance in real-time

Bachelors in Technology (B. Tech)

Electronics and Communications Engineering Dept., 

Vasireddy Venkatadri Institute of Technology (VVIT), Guntur

15/09/2009 - 15/05/2013

Postdoctoral Researcher

UM-SJTU Joint Institute, 

Shanghai Jiao Tong University, Shanghai, China

28/11/2024 - Present

• Propose and implement the Reliability-Aware In-Memory Computing (IMC)

ASIC DESIGN ENGINEER

SEMICON BU., 

CYIENT Limited, Hyderabad

15/07/2022 - 27/09/2024

• Developed gm/ID design methodology for analog circuit design using octave/matlab tool

• Designed Low Dropout Voltage (LDO), Op-amp (comparator) circuits at TSMC 65nm technology

• Designing and Implementing circuits (such as SAL) in Receiver path of High Bandwidth Memory

• Developed under- and over-voltage monitor circuits in the Supply block of SoC

• Worked as AMS verification Engineer on various PMIC blocks 

Research Associate

Department of Civil Engineering

Shiv Nadar University, NCR-Delhi

01/01/2022 - 03/04/2022

• Designed and implemented Arduino-based embedded hardware for collecting Agricultural data from wheat crop field

• Worked on an artificial neural network (ANN) model for Crop Yield Prediction

Gradute Teaching Assistant 

Department of Electrical Engineering

Shiv Nadar University, NCR-Delhi

01/01/2017 - 15/05/2022

Assisted faculties in laboratory research and aided students during review sessions for the following courses:

• EED401—VLSI Design and Technology (SP 2018, SP 2019, SP 2020, SP 2021) 

• EED361—Analog CMOS VLSI Design (MN 2019, MN 2020)

• EED359—Digital System Design with FPGAs (SP 2017, SP 2020) 

• EED308—Embedded Systems Hardware (SP 2019, SP 2020)

• EED363—Applied Machine Learning (SP 2021)

• EED206—Digital Electronics (MN 2019, MN 2020, MN 2021)

• EED204—Analog Electronics (MN 2018, MN 2021)

• EED103—Basic Electrical Engineering (MN 2018, MN 2020, MN 2021)

Gradute Teaching Assistant

Department of Electronics and Communication Engineering

National Institute of Technology, Hamirpur

15/07/2014 - 24/04/2016

Assisted professors and aided students in the laboratory for the following courses:

• Microcontroller and Embedded Systems (SP 2016)

• CAD of Integrated Circuits (SP 2015)

• Basic Electrical Engineering (MN 2014, MN 2015)

1. VLSI Circuit Simulation:                    Cadence-Virtuoso, Synopsys H-SPICE, LT-SPICE

2. Layout Editor:                                     Cadence-Layout XL, Tanner Layout

3. RTL Synthesis:                                   Xilinx Vivado Design Suite, Modelsim

4. Physical Designing:                          Cadence Genus, Innovus, Tempus

5. Hardware Description Language:  Verilog, basics of VHDL, SystemVerilog, Verilog-A

6. Hardware Handled:                           FPGA (ZYBO, Nexys4), STM32, Arduino, DSO

7. Device Modelling:                             Synopsis Sentaurus TCAD

8. Programming Languages:              C, C++, Python, Matlab code

9. Software Handled:                           MS Office Tools, Origin Software, MATLAB, Latex

10. Operating Systems:                         Windows, Linux (Ubuntu and RHEL)

• Best oral presentation in the session and awarded travel grant in iSES-2018 conference

• Research Fellowship from Shiv Nadar University, India

• Teaching Assistantship from MHRD, India—NIT Hamirpur

• Qualified GATE Entrance Test in 2013, 2014, 2015

• Won prizes in technical quizzes at various college festivals. 

• Won second prize at project-expo, VIVA VVIT 2012 

• "Grand Challenge: LLM-Based Analog Circuit Design Competition", organized by IEEE AICAS Grand Challenge team

• "Short Course in Modeling and Simulation of Nano Transistors," organized by Nanolab @IIT Kanpur

  • • Participated in the workshop to learn different aspects of nanotransistors, such as compact modeling, TCADsimulations, and electrical characterization

    • Trained in different Electronic Design Automation (EDA) tools

• "Tutorial Session in Neuromorphic Devices," organized by ICEE 2020 at IIT Delhi

  • • Participated in a tutorial session on the importance of neuromorphic computing in today’s world and how emerging devices are part of next-generation computing

• "Physical Design and Verification Internship Program," organized by Entuple Technologies Pvt. Ltd.

  • • Executed the RTL and Physical Synthesis flow of UART using Cadence Genus

    • Carried out static timing analysis (STA) using the Cadence Tempus tool

    • Performed physical design analysis for the I2C netlist using the Cadence Innovus tool

    • Completed internship and earned a STAR certificate for achieving a good grade in quizzes and assignments

• "Indian Nanoelectronics User Program (INUP) Workshop," organized by Centre for Nanoscience and Engineering (CeNSE)-IISC Bangalore, March 2015

• "ARM university competition," organized by the National Institute of Technology-Hamirpur.

• IEEE Membership since 2018

• Reviewed and assessed the quality of manuscripts for the following journals/conferences:

International Journals

• • • • Integration, the VLSI Journal

      • IEEE Transactions of Very Large Scale of Integrations (TVLSI)

      • International Journal of Circuit Theory and Applications

      • The Journal of Supercomputing

      • Journal of Circuits, Systems, and Computers (JCSC)

      • IET Circuits, Devices & Systems

      • Analog Integrated Circuits and Signal Processing

International Conferences

• • • • Third International Conference on Computing and Network Communications (CoCoNet'19), 2019

      • International Conference on Modelling Simulation & Intelligent Computing, 2020

      • IEEE International Midwest Symposium on Circuits and Systems, 2022 and 2024,  2025

      • IEEE International Symposium on Circuits and Systems, 2025

      • IEEE Interregional NEWCAS Conference, NEWCAS, 2025

      • IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM, 2025

      • IEEE Custom Integrated Circuits Conference (CICC), 2025

      • IEEE International Symposium on Quality Electronic Design, ISQED, 2025