Publications

Fields of Intrest

Computer Architecture & Systems
Hardware for Approximate Computing
Digital VLSI Design & FPGA-based systems

Google Scholar Profile

Saurabh Singh‪Georgia Institute of Technology‬ - ‪‪Cited by 33‬‬ - ‪Computer Architecture‬ - ‪Hardware Security‬ - ‪Approximate Computing‬

Conference Papers

Vishesh Mishra, Sparsh Mittal, Saurabh Singh, Divy Pandey, Rekha Singhal, "MEGA-MAC: A Merged Accumulation based Approximate MAC Unit for Error Resilient Applications" in the proceedings of the Great Lakes Symposium on VLSI (GLSVLSI) 2022, Irvine, CA, USA. DOI: 10.1145/3526241.3530384
Sagar Satapathy, Saurabh Singh, Vishesh Mishra, Divy Pandey, Kaustav Goswami, Dip Sankar Banerjee, "AxLEAP: Enabling Low-Power Approximations Through Unified Power Format" to appear at IEEE International Symposium on Circuits & Systems (ISCAS-2022), Austin, Texas, USA.
Vishesh Mishra, Divy Pandey, Saurabh Singh, Sagar Satapathy, Kaustav Goswami, Babita Jajodia, Dip Sankar Banerjee, "ART-MAC: an Approximate Rounding and Truncation Based Mac Unit for Fault-Tolerant Applications" to appear at IEEE International Symposium on Circuits & Systems (ISCAS-2022), Austin, Texas, USA.
Saurabh Singh, Vishesh Mishra, Sagar Satapathy, Divy Pandey, Kaustav Goswami, Dip Sankar Banerjee, and Babita Jajodia, “EFCSA: An Efficient Carry Speculative Approximate Adder with Rectification” to appear at 23rd International Symposium on Quality Electronic Design (ISQED-22), California, USA. DOI: 10.1109/ISQED54688.2022.9806249
Divy Pandey, Vishesh Mishra, Saurabh Singh, Sagar Satapathy, Babita Jajodia, and Dip Sankar Banerjee, “HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications” to appear at 23rd International Symposium on Quality Electronic Design (ISQED-22), DOI: 10.1109/ISQED54688.2022.9806220 Santa Clara, CA, USA.
Divy Pandey, Saurabh Singh, Vishesh Mishra, Sagar Satapathy, and Dip Sankar Banerjee, "SAM: a Segmentation Based Approximate Multiplier for Error Tolerant Applications" accepted at IEEE International Symposium on Circuits and Systems (ISCAS), 2021, Daegu, KOREA. DOI: 10.1109/ISCAS51556.2021.9401266 [Global Flagship Conference of IEEE Circuits and Systems (CAS)]. [paper] [Slides]
Rajat Bhattacharjya, Vishesh Mishra, Saurabh Singh, Kaustav Goswami, and Dip Sankar Banerjee. "An Approximate Carry Estimating Simultaneous Adder with Rectification" in Proceedings of 2020 on Great Lakes Symposium on VLSI (GLSVLSI '20). Association for Computing Machinery, New York, NY, USA, 139–144. DOI: 10.1145/3386263.3406928 [Best Paper Award - 2nd place] [paper] [slides]

Short Papers / Research Posters

Divy Pandey, Vishesh Mishra, Saurabh Singh, Sagar Satapathy, and Babita Jajodia, "HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications" accepted at the 13th IEEE High-Performance Computing (HiPC), Student Research Symposium (SRS), 2021, Bangalore, India. [Best Poster Award] [link] [slides]
Rajat Bhattacharjya, Vishesh Mishra, Saurabh Singh, and Kaustav Goswami, "ACEP: An Accuracy-Configurable Carry Estimating Parallel Adder", accepted in 12th HiPC Student Research Symposium(SRS), 2019, Hyderabad, India. [Best Poster Award] [link] [poster]
Vishesh Mishra, Divy Pandey and Saurabh Singh "CEAPA: A Carry Estimating Approximate Parallel Adder", accepted at Research Conclave, 2020 Edition, IIT Guwahati.