Description

RISC-V Atom project consists of an embedded class soft-core processor and a complete software development environment that is built around it. RISC-V Atom is proven on silicon in the form of HydrogenSoC which was implemented on a Xilinx Spartan-6 FPGA board clocked at 50Mhz.

This project is open-source under the MIT license!

Description

This project involves developing a platform to deploy approximate arithmetic circuits in fault-tolerant applications at the SoC level. This is achieved by implementing a custom non-standard extension to the RISC-V ISA called the 'X' extension. Furthermore, a C/Assembly level library called 'Axkit' was also developed in order to abstract the use of the 'X' approximate computing hardware with the help of the 'X' extension.

This project will be open-source very soon!

This project will be open-source very soon!

Collaborators

• Hariharan O J, NIT Trichy.

• Prathmesh, BITS Pilani.

Supervisors

• Dr. V. Kamakoti, Professor,  CSE Dept, Indian Institute of Technology Madras, India.

• Arjun Menon, Chief Engineer, InCore Semiconductors.

Description

We, a team of three members contributed to the development of a side-channel attack resilient Elliptic Curve Cryptography (ECC) co-processor for the Shakti series of processors. Shakti is India's first indigenous processor development program. 

My part was to implement a parametrized finite-field hybrid Karatsuba multiplier in Bluespec SystemVerilog. A 233-bit instance of the multiplier was used in an ALU to carry out ECC operations in the co-processor. 

Description

I was part of a robotics group where we designed & built a battle robot named "Brahmaputra". We participated in the 30 lbs category of the International Robowars event organized during Tech Fest-19 (IIT Bombay).

Collaborators

• Divy Pandey, ECE Dept, Indian Institute of Information Technology Guwahati, India

• Vishesh Mishra, ECE Dept, Indian Institute of Information Technology Guwahati, India

• Sagar Satapathy, CSE Dept, Indian Institute of Technology Jodhpur & Synopsys India

• Kaustav Goswami, University of California Davis, USA

Supervisor

• Dip Sankar Banerjee, Assistant Professor, CSE Dept, Indian Institute of Technology Jodhpur, India

Abstract

In recent times, approximate computing has found significant use in applications that can tolerate partially inaccurate results. This tolerance can be exploited to design simpler hardware aimed at getting area and energy benefits. In this work, we propose a novel technique to multiply two unsigned binary numbers through a Segmentation based Approximate Multiplier (SAM). The proposed design reduces the size of the Partial Products Matrix (PPM) in the order of n × (2n — 1) to a Reduced Partial Product Matrix (R-PPM) of the order 4 × 2n. Additionally, it also eliminates the extra hardware required for compression and rearrangement of partial products. μ-SAM, an optimized version of our basic design is also proposed along with this work. μ-SAM further minimizes the on-chip area and power consumption of the basic design. The basic design consumes 32.43% lesser on-chip area when compared to the conventional Wallace tree multiplier [1] and produces results that are 89.1% more accurate when compared to other existing state-of-the-art designs such as TOSAM [2], LETAM [3], and DQ4:2C4 [4].

Collaborators

• Rajat Bhattacharjya, ECE Dept, Indian Institute of Information Technology Guwahati, India

• Vishesh Mishra, ECE Dept, Indian Institute of Information Technology Guwahati, India

• Kaustav Goswami, University of California, Davis, USA

Supervisor

• Dr. Dip Sankar Banerjee, Assistant Professor, CSE Dept, Indian Institute of Technology Jodhpur, India

Abstract

Approximate computing has in recent times found significant applications towards lowering power, area, and time requirements for arithmetic operations. Several works done in recent years have furthered approximate computing along these directions. In this work, we propose a new approximate adder that employs a carry prediction method. This allows parallel propagation of the carry allowing faster calculations. In addition to the basic adder design, we also propose a rectification logic which would enable higher accuracy for larger computations. Experimental results show that our adder produces results 91.2% faster than the conventional ripple-carry adder. In terms of accuracy, the addition of rectification logic to the basic design produces results that are more accurate than state-of-the-art adders like SARA and BCSA by 74%.