Saurabh Singh
Hi, Welcome to my webpage!
I am a first-year Ph.D. Student Computer Science at the School of Computer Science at Georgia Tech. At Tech, I am part of the HPArch Lab advised by Prof. Hyesoon Kim.
Previously, I was working as a full-time ASIC-Design Engineer at SiFive. I have completed my undergrad (B. Tech) in Electronics and Communication Engineering (ECE) at the Indian Institute of Information Technology Guwahati (IIITG), India.
Feel free to navigate around!
About Me
Research Interests & Experience
I am broadly interested in the domain of Computer Architecture and Hardware Security. Recently I've been focussing on Security and Memory Safety in GPUs.
My past research lies broadly in the domain of Computer Architecture, Systems, and Digital VLSI design.
During my undergrad, I worked on the design, implementation, and evaluation of approximate arithmetic circuits such as Adders, Multipliers, and Multiply and Accumulate (MAC) units. These were designed to achieve better area, power, and timing parameters than their accurate counterparts, while at the same time, maintaining a respectable quality of results on fault-tolerant applications like image processing and machine learning.
I am also a RISC-V enthusiast, checkout RISC-V Atom, a RISC-V SoC platform that I've been working on.
My bachelor's thesis was called "CLAP: Cross-Layer Approximate Computing on Custom RISC-V Processors" as a part of which I modified the Atom processor to incorporate a tightly integrated approximate computing unit. The system was capable of executing approximate computing instructions natively using a non-standard extension to the RISC-V ISA. I also worked on adding support for a C & assembly library called AxKit.
My undergraduate research has been supervised by Dr. Dip Sankar Banerjee (Assistant Professor, CSE Dept, Indian Institute of Technology Jodhpur) and Dr. Babita Jajodia (Assistant Professor, ECE Dept, Indian Institute of Information Technology Guwahati).
Education
- Georgia Institute of Technology
Atlanta, GA, USA | 2023 - Present
Doctor of Philosophy (Ph.D.) in Computer Science
- Indian Institute of Information Technology Guwahati
Guwahati, Assam, India | 2018 - 2022
Bachelor of Technology (B. Tech.) in Electronics and Communication Engineering
Work Experience
Full Time
ASIC Design Engineer, SiFive India Pvt. Ltd.
Design Engineer, InCore Semiconductors Pvt. Ltd.
Internships
GPU Design Intern, HPArch Lab, Georgia Tech.
Hardware Design Intern, IIIT Delhi.
Crypto-Hardware Design Intern, RISE Lab, IIT Madras.
Highlights
Aug. 2023: Started Ph.D. in Computer Science at Georgia Tech.
Aug. 2022: Started a full-time role as an ASIC Design Engineer at SiFive.
Jun. 2022: Started a full-time role as a Design Engineer at InCore Semiconductors.
Dec. 2021: Our paper titled "An Efficient Carry Speculative Approximate Adder with Rectification" was accepted at the 23rd International Symposium on Quality Electronic Design (ISQED-22), California, USA.
Dec. 2021: Our paper titled "HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications" was accepted at the 23rd International Symposium on Quality Electronic Design (ISQED-22), California, USA.
Dec. 2021: Our paper titled "HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications" was awarded the best poster award at HiPC 2021, Student Research Symposium (SRS).
Nov. 2021: Our paper titled "HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications" was accepted at the HiPC 2021, Student Research Symposium (SRS) for a poster presentation.
Jan. 2021: Our paper titled "SAM: a Segmentation Based Approximate Multiplier for Error Tolerant Applications" was accepted at ISCAS-2021.
Sep. 2020: Our paper titled "An Approximate Carry Estimating Simultaneous Adder with Rectification" was awarded the Best Paper Award [2nd place] at GLSVLSI 2020.
Mar. 2020: Our paper titled "An Approximate Carry Estimating Simultaneous Adder with Rectification" was accepted at GLSVLSI 2020.
Dec. 2019: Our poster titled "ACEP: An Accuracy-Configurable Carry Estimating Parallel Adder" was awarded the best poster award in HiPC 2019, Student Research Symposium (SRS).
Nov. 2019: Our poster titled "ACEP: An Accuracy-Configurable Carry Estimating Parallel Adder" was accepted at HiPC 2019, Student Research Symposium (SRS) for a poster presentation.
Aug. 2018: Started B.Tech in Electronics and Communication Engineering at IIIT Guwahati.
Contact
Work Address
HPArch Lab, Georgia Tech
266 Ferst Drive, KACB 2337
Atlanta, GA 30332-0765
