eRISC
A 16-bit ISA for embedded class processors
Collaborators
Divy Pandey, ECE Dept, Indian Institute of Information Technology Guwahati
Vishesh Mishra, ECE Dept, Indian Institute of Information Technology Guwahati
Siddharth Rajawat, ECE Dept, Indian Institute of Information Technology Guwahati
Supervisors
Dr. Babita Jajodia, Assistant Professor, ECE Dept, Indian Institute of Information Technology Guwahati, India
Dr. Dip Sankar Banerjee, Assistant Professor, CSE Dept, Indian Institute of Technology Jodhpur, India
We Intend to open-source this project soon!
Sub-Projects
eRISC
Embedded RISC Instruction Set Architecture
eRISC (short for Embedded RISC) is a novel royalty-free 16-bit Instruction Set Architecture (ISA) that is set for catering to small-scale embedded applications. eRISC is a complete ISA with almost all the instructions that are found in industry-standard ISAs. eRISC is designed to have high code density and modular architecture.
Charon
The eRISC ISA Simulator
Charon, the eRISC-V ISA Simulator, simulates a functional model of an eRISC processor at the software level. It is written entirely in C++ hence achieving a very fast simulation rate. Charon has the ability to dump its simulation results onto the console as well as into a log file. It uses the Pluto disassembler for run-time instruction disassembly.
eRISC Assembler
Assembler for the eRISC ISA
eRISC Assembler is a tool to convert the code written in eRISC assembly language to ELF executable files. It is a two-pass assembler that is written entirely in C++.