During my time as a research intern at IIT Hyderabad I was immersed in a project that centers on numerical algorithms and their Verilog implementations. My primary focus encompasses the implementation of Volder's Algorithm (CORDIC), Newton Raphson method for Reciprocal. I've also successfully implemented modules for adding and subtracting numbers in Q.I.F format, MAC (Multiplier and Accumulator) and streaming accumulator. My work also extends to the implementation of IIR and FIR filters, all meticulously designed in Verilog. I also implemented a naive version of PSS (Primary Synchronization Signal) in Verilog.

Owing to this experience, I decided to build an IEEE Floating Point Unit. You could check it out Projects section!