CS203: Digital Logic Design
Overview
The objective of the course:
A) To learn fundamentals of digital design, including boolean algebra, basic gates, logic minimization, finite state machines, state minimization.
B) To learn to design standard logic blocks like arithmetic operations, encoders, multiplexers, counters, registers using basic logic gates
C) To learn to analyze a digital system for area and delay
D) To learn to design a digital system using basic gates, standard logic blocks. Digital systems may be combinational or sequential or both
Prerequisite:
Almost none.
Syllabus
Module 1 Introduction (2 weeks): Introduction to digital systems and motivation for digital design. number systems:integer, floating point, codes
Module 2 Boolean algebra, logic gates and minimization (2 weeks) : Boolean equations, algebra, K-maps and QM minimization, multi-level logic minimization
Module 3 Combinational logic design (2 weeks) : Multiplexers, decoders, encoders, arithmetic circuits. designing using standard blocks
Module 4 Sequential building blocks(2 weeks) : Latch, flip-flop, counters, registers, memories
Module 5 Synchronous Sequential system design (3 week) : State machines design, analysis, SM charts. Top down approach
Module 6 Technology (1 weeks) : FPGA, Synthesis flow, automation
Verilog hardware description language would be used to demonstrate few concepts and as the design language during lab experiments.
Logistics:
We would be following flipped mode in the course
Lectures of the week will be uploaded on Monday, 9AM. Students are supposed to go through the lectures by Wednesday.
Thursday and Friday lectures will be used for discussion, problem solving, and tutorials. These classes will not be recorded.
Every week there will be a quiz, usually during the lecture hours.
Google classroom will be used for discussion and uploading lectures
Moodle will be used for quizzes, class test and assignment upload.
If you want to one-to-one discussion with instructor or TA, send an email to get the appointment
Class -interactions:
Wednesday : 3:00 pm to 3:50 pm
Thursday : 3:00 pm to 3:50 pm
Friday : 3:00 pm to 3:50 pm
Google meet :
https://meet.google.com/bbz-osvj-bgx
Instructor
Dr. Neeraj Goel (neeraj@iitrpr.ac.in)
TA:
Schedule
Course duration is August 3, 2021 to Nov 27, 2021. The schedule will be populated as we go.
Week 1: Aug 3, 2021
M1.01 Introduction (25 Minutes)
M1.02 Analog vs Digital (34 Minutes)
M1.03 Binary number system (44 Minutes)
M1.04 Negative number system (52 Minutes)
Week 2: August 9, 2021
M1.05 Other number systems (36 minutes)
M1.06 Floating point numbers (52 Minutes)
M1.07 Floating point numbers, part 2 (51 Minutes)
M1.08 Floating point - supplementary (27 Minutes)
Week 3: August 16, 2021
August 19 (Thursday) - public holiday
M2.01 Boolean algebra (51 Minutes)
M2.02 Boolean algebra - 2 (43 minutes)
M2.03a Canonical form (34 minutes)
Week 4: August 23, 2021
M2.03b Boolean minimization (17 minutes)
M2.04 Gates (27 Minutes)
M2.04b-Verilog HDL (44 minutes)
M2.05 K-maps (43 minutes)
Week 5: August 30, 2021
M2.06 QM method (43 minutes)
M2.07 Multi-level logic and gate delay (56 minutes)
M3.01 Multiplexers (42 minutes)
Week 6: Sept 6, 2021
Sept 10 (Friday) - public holiday
M3.02 De-multiplexers (48 minutes)
M3.03 Decoders (47 minutes)
Week 7: Sept 13, 2021
M3.04 Programmable hardware (37 minutes)
M3.05 Adders (59 minutes)
M3.06 Fast adders (48 minutes)
Week 8: Sept 20, 2021
Sept 21 - Thursday time table
Sept 22 - Friday timetable
Sept 23 - No class
M3.Multiplication (37 minutes)
M3.08 Iterative circuits (51 minutes)
Revision
Sept 27, 2021
Mid-term week
Week 9: Oct 4, 2021
M4.01 Latch (53 minutes)
M4.02 D-Flip-flop (32 minutes)
M4.03 Other flip-flops (29 minutes)
M4.Verilog (55 minutes)
Week 10: Oct 11, 2021
Oct 15 (Friday) public holiday
M4.04 Counters (32 minutes)
M4.05 Registers (64 minutes)
Week 11: Oct 18, 2021
Oct 19 - Tuesday (Public holiday)
Oct 20 - Friday timetable
M4.06 Memory (40 minutes)
Verilog behavior model
Week 12: Oct 25, 2021
M5.01 Sequential circuit analysis (32 minutes)
M5.02 Building state graph (37 minutes)
M5.03 Sequence detector (49 minutes)
Week 13: Nov 1, 2021
Nov 4 (Thu) - Public holiday - Diwali week
M5.04 State machine reduction (44 minutes)
M5.05 Sequential addition (44 minutes)
Week 14: Nov 8, 2021
M5.06 Multiply and divide (42 minutes)
M5.07 Interacting state machine (30 minutes)
M5.08 RTL design (47 minutes)
Week 15: Nov 15, 2021
Nov 19 (Friday) - public holiday
M5.09 RTL- Example 1
M5.10 RTL - Example 2
Week 16: Nov 22, 2021
M6.01 FPGA (57 minutes)
M6.02a FPGA design flow (27 minutes)
M6.02b FPGA demo (31 minutes)
M6.03 ASIC design flow (39 minutes)
M6.03b Future directions (18 minutes)
Nov 29, 2021
End term exam
Grading scheme for CS203
Grading scheme assuming end term exam will be offline.
Quizzes (15%)
Each week there will be a quiz, with a maximum of 14.
Best 75% would be considered for final evaluation. If 75% is not an integer, floor would be taken.
If end-term exam is online, quiz marks will increase from 15 to 25.
Mid-term exam (25%)
Lab assignments (25%): Most of the lab exercises will be in Verilog HDL. Lab exercises will also include a course project.
End term exam (35%): If end term exam is online, its weightage will be reduced to 25%
General guidelines:
- All the lab submissions should be on time. Delayed submission will attract penalty at the rate of 10% per day. After delay of 10 days, no marks will be given to a assignment.
- Plagiarism of any sort (from internet resource or from friends) will be heavily penalized. In case, the case of copy is from other students of the course, both parties will get negative marks equal to double the weightage of assignment/submission. In second instance will be given F. The copy case will also be notified to the department for records.
Books
First one will be used for most of the topics, some topics will be covered from other books
1. Fundamentals of Logic Design By Charles H. Roth, Jr., Larry L Kinney, 7th edition
2. Digital design by Morris Mano and M.D. Ciletti, 6th edition, published by Pearson
3. Switching and Finite Automata theory by Kohavi and Jha, 3rd edition.
4. Digital Systems Design Using Verilog By Charles Roth, Lizy K. John, Byeong Kil Lee