CS204: Computer Architecture

CS204: Computer Architecture

Objective of the course:

A) Understand ISA of a processor and Learn assembly language

B) Design of micro-architecture of a processor

C) Memory hierarchy - caches, main memory, virtual memory and secondary memory


Prerequisite:

Digital design (combination and sequential design)

Syllabus

Module 1 Introduction: Introduction to ISA and processor architecture. Performance measurement

Module 2 Instructions and Assembly language: Understand different instructions, syntax, semantics and encoding. Using instructions to write assembly programs. Programming using Venus simulator

Module 3 Micro-architecture: Design of single cycle and piplelined processor

Module 4 Caches and memory hierarchy: Caches, main memory, virtual memory.

Module 5 Storage : solid state drives

Module 6 Input/Output and advanced architectures

Logistics:

Class timings:

  • Wednesday 2:00 pm to 2:50 pm

  • Thursday 2:00 pm to 2:50 pm

  • Friday 2:00 am to 2:50 pm

TA:

To be announced

Office hours:

  • Send an email to get the appointment

Digital platforms

Google classroom for assignment submission, discussions and distribution of notes/videos

This website for general information/announcements

Class Schedule

  • Week 1 :Jan 2, 2022

    • Class starts on Jan 3

    • L1 (Jan 4) - Introduction - computers and processor - why this course

    • L2 (Jan 5) - Compiler, compilation and performance

    • L3 (Jan 6) - performance and technology

  • Week 2 : Jan 9, 2022

    • L4 (Jan 11) - ISA, Design of ISA

    • L5 (Jan 12) - ISA - instructions - arithmetic

    • L6 (Jan 13) - ISA - instructions - branch instructions

  • Week 3 : Jan 16, 2022

    • Jan 20 - SA activity - No class day

    • L7 (Jan 18) - ISA - load store

    • L8 (Jan 19) - ISA - functions

  • Week 4: Jan 23, 2022

    • CCM1

    • Jan 26 - Public holiday

    • L9 (Jan 25) : - ISA - recursive calls

    • L10 (Jan 27): - ISA privileged instructions

  • Week 5 : Jan 30, 2022

    • L11 (Feb 1): ISA encoding

    • L12 (Feb 2): Processor design - Memory, register files

    • L13 (Feb 3): Processor design - Single cycle model

  • Week 6 : Feb 6, 2022

    • L14 (Feb 8): Processor design Single cycle model

    • L15 (Feb 9): Pipeline basic - timing diagrams

    • L16 (Feb 10): Pipelined processor design

  • Week 7 : Feb 13, 2022

    • L17 (Feb 15) : Dependencies

    • L18 (Feb 16): Bypass/forwarding

    • L19 (Feb 17): Branch prediction

  • Week 8 : Feb 20, 2022

    • Feb 21 (Tue) - Friday timetable

    • L20 (Feb 21) - Software solutions

    • L21 (Feb 22) - Buffer 1

    • L22 (Feb 23) - Buffer 2

    • L23 (Feb 24) - Buffer 3

  • Week 9 : Feb 27, 2022

    • Mid term exam week

  • Week 10 : March 6, 2022

    • March 6 (Mon) no class

    • March 8 (Wed) - Holi - Public holiday

    • L24 (March 9):

    • L25 (March 10):

  • Week 11 : March 13, 2022

    • CCM II

    • L26 (March 15):

    • L27 (March 16):

  • Week 12 : March 20, 2022

    • L28:

    • L29:

    • L30:

  • Week 13: March 27, 2022

    • L31 :

    • L32:

    • L33:

  • Week 14: April 3, 2022

    • April 4 (Tuesday) - public holiday

    • April 7 (Friday) - public holiday

    • L34:

    • L35:

  • Week 15: April 10, 2022

    • April 14 (Friday) - Public holiday

    • L36

    • L37:

  • Week 16: April 17, 2022

    • April 20 (Thursday) will work as Friday timetable

    • L38:

    • L39:

    • L40:

  • Week 17: April 24, 2022

    • April 27 - last day of class

    • April 29 - End sem exam starts

    • L41:

    • L42:

  • Week 18: May 2, 2022

    • End term exam (May 2 to May 11)

Grading scheme

  • Mid term (30%)

  • End term (30%)

  • Lab and project (30%)

  • Class-participation/In-class Quizzes (10%)

    • 75% of in-class quizzes will be considered

General guidelines:

- All the submissions should be on time. Delayed submission will attract penalty at the rate of 10% per day. After delay of 10 days, no marks will be given to a assignment.

- Plagiarism of any sort (from internet resource or from friends) will be heavily penalised. In case, the case of copy is from other students of the course, both parties will get negative marks equal to double the weightage of assignment/submission. In second instance (across your studentship at IIT Ropar) will be given F.

Books

Text Books

  1. Computer Organization and Design RISC-V Edition: The Hardware Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design) by David A. Patterson (Author), John L. Hennessy (Author)

  2. Basic Computer Architecture, Version 2.1 by Smruti R. Sarangi