EE656: CAD FOR VLSI DESIGN

Logistics:

Class timings:

• Wednesday, 2 - 3pm

• Thursday, 2 - 3pm

• Friday, 2 - 3 pm

Classes would happen online over google meet. Recording would be shared.

Google Meet joining info

Video call link: https://meet.google.com/yaz-pvsk-mhm

TA:

Office hours:

• Send an email to get the appointment

Digital platforms

• Moodle for class tests and assignment submissions.

• Google classroom for discussions, announcements and distribution of notes/videos

Class Schedule (Tentative)

Course duration is August 3, 2021 to Nov 27, 2021. The tentative schedule is as follows. A few topics may be added or removed based on class progress

• Week 1: Aug 3, 2021

  • Digital design - need for automation, requirement of this course

  • Revision of digital design - boolean algebra, gates and flip-flops

  • Sequential design - state machines

• Week 2: August 9, 2021

  • RTL design - GCD

  • Example 2: Bubble sort

  • Example 3: Traffic light

• Week 3: August 16, 2021

  • August 19 (Thursday) - public holiday

  • Verilog - basic (two lectures)

• Week 4: August 23, 2021

  • Verilog (three lectures)

• Week 5: August 30, 2021

  • Designing a processor in verilog (three lectures)

• Week 6: Sept 6, 2021

  • Sept 10 (Friday) - public holiday

  • Verification - writing test-bench (two lectures)

• Week 7: Sept 13, 2021

  • Specification in higher abstraction level - C/C++/domain specific language (three lectures)

• Week 8: Sept 20, 2021

  • Sept 21 - Thursday time table

  • Sept 22 - Friday timetable

  • Sept 23 - No class

  • Pipelining and parallelism

  • Revision

• Sept 27, 2021

  • Mid-term week

• Week 9: Oct 4, 2021

  • Behavior synthesis - input and output

  • Scheduling - ASAP/ALAP/LIST

• Week 10: Oct 11, 2021

  • Oct 15 (Friday) public holiday

  • Scheduling - multi-cycle, pipelining

• Week 11: Oct 18, 2021

  • Oct 19 - Tuesday (Public holiday)

  • Oct 20 - Friday timetable

  • Resource allocation and resource binding

• Week 12: Oct 25, 2021

  • Logic synthesis - Two level logic optimisation QM and optimization problem

• Week 13: Nov 1, 2021

  • Nov 4 (Thu) - Public holiday - Diwali week

  • Multi-level logic synthesis and cell binding

• Week 14: Nov 8, 2021

  • Floorplanning, placement

• Week 15: Nov 15, 2021

  • Nov 19 (Friday) - public holiday

  • Optimization problem : GA, stimulated annealing, ACO

• Week 16: Nov 22, 2021

  • Routing

  • FPGA - placement and routing

• Nov 29, 2021

  • End term exam

Assignments

Assignment 1 : Paper and pen design assignment : start date 13 August, deadline 30 August.

Assignment 2 : Single cycle processor design in Verilog : Start date August 3, Deadline Oct 4

Assignment 3: Verification of processor RTL: Start date Oct 4. Deadline October 18

Assignment 3: Pipelined processor design in Verilog . Start date : October 18. Deadline Nov 1

Assignment 4: Design FIR/IIR/MM in C using Vivado-HLS. Start date Nov 8, deadline Nov 23

Grading scheme

• Mid term (25%)

• End term (35%)

• Project/assignments (25%)

• In-class Quizzes (10%)

  • There would be a small quiz (2-4 minutes) in every class. Best 75% of them would be considered for evaluations.

• In case end term is online, quizzes weight will increase from 10 to 20, and end term weight will reduce from 35 to 25.

General guidelines:

- All the submissions should be on time. Delayed submission will attract penalty at the rate of 10% per day. After delay of 10 days, no marks will be given to a assignment.

- Plagiarism of any sort (from internet resource or from friends) will be heavily penalised. In case, the case of copy is from other students of the course, both parties will get negative marks equal to double the weightage of assignment/submission. In second instance will be given F.

Books

Text Books

No single text book.

Reference Books

Digital design: Fundamentals of Logic Design By Charles H. Roth, Jr., Larry L Kinney, 7th edition

Verilog: Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition By Samir Palnitkar

Processor: Computer Organisation & Architecture by Smruti Ranjan Sarangi

Behavior and logic synthesis: Synthesis and optimization of digital circuits by Giovanni De Micheli

Physical synthesis: Algorithms for VLSI Physical Design Automation by Naveed Sherwani