CS204: Computer Architecture

Objective of the course:

A) Use knowledge of RISCV ISA to: Given a "C" code, students should be able to

Given a C code, write assembly program in RISCV machine code
Optimize assembly code by using addressing mode efficiently, memory optimization, branch optimization.
Trace assembly programs to debug, and estimate performance.

B) Design micro-architecture of a processor for a given ISA

Single cycle, as well as pipelined implementation
Calculate the impact of micro-architecture artefacts, like pipeline, forwarding, and branch prediction on performance of an assembly code snippet

C) Use understanding of memory hierarchy (registers, caches, main memory, virtual memory and secondary memory) to

Calculate impact of memory access patterns on performance
Design memory hierarchy for a memory access pattern

Prerequisite:

Digital design (combination and sequential design)

Syllabus

Module 1 Introduction: Introduction to ISA and processor architecture. Performance measurement

Module 2 Instructions and Assembly language: Understand different instructions, syntax, semantics and encoding. Using instructions to write assembly programs. Programming using Venus simulator

Module 3 Micro-architecture: Design of single cycle and piplelined processor

Module 4 Caches and memory hierarchy: Caches, main memory, virtual memory.

Module 5 Storage : solid state drives

Module 6 Input/Output and advanced architectures

Logistics:

Class timings:

Wednesday 2:00 pm to 2:50 pm
Thursday 2:00 pm to 2:50 pm
Friday 2:00 am to 2:50 pm

TA:

To be announced

Office hours:

Send an email to get the appointment

Digital platforms

Google classroom for assignment submission, discussions and distribution of notes/videos

This website for general information/announcements

Class Schedule

Week 1 :Jan 5, 2026
- Class starts on Jan 5
- L1 (Jan 7) - Introduction - computers and processor - why this course
- L2 (Jan 8) - Compiler, compilation and performance
- L3 (Jan 9) - performance and technology
Week 2 : Jan 12, 2026
- L4 (Jan 14) - ISA, Design of ISA
- L5 (Jan 15) - ISA - instructions - arithmetic
- L6 (Jan 16) - ISA - instructions - branch instructions
Week 3 : Jan 19, 2026
- L7 (Jan 21)
- L8 (Jan 22) - ISA - load store
- L9 (Jan 23) - ISA - functions
Week 4: Jan 26, 2026
- Lab Test 1 - simple function or no functions
- L10 (Jan 28) : - ISA - recursive calls
- L11 (Jan 29): - ISA privileged instructions
- L12 (Jan 30)
- L13 (Jan 31) - Sat as Friday
Week 5 : Feb 2, 2026
- L14 (Feb 4): ISA encoding
- L15 (Feb 5): Processor design - Memory, register files
- Feb 6 : Student activity
Week 6 : Feb 9, 2026
- L16 (Feb 11): Processor design Single cycle model
- L17 (Feb 12): Pipeline basic - timing diagrams
- L18 (Feb 13): Pipelined processor design
Week 7 : Feb 16, 2026
- Lab test 2 - recurresive functions
- L19 (Feb 18) : Dependencies
- L20 (Feb 19): Bypass/forwarding
- L21 (Feb 20): Branch prediction
Week 8 : Feb 23, 2026
- Mid term exam week
- Lab test 3 - recursive test
Week 9: March 2, 2026
- March 4 - Holi
- March 5 - project evaluation
- L22 (March 6 )
Week 10 : March 9, 2026
- L23 (March 11)
- L24 (March 12)
- (March 13): Student affair activity
Week 11 : March 16, 2026
- Lab test 4 - PIN
- L25 (March 18):
- L26 (March 19):
- March 20 - student affair activity
Week 12 : March 23, 2026
- L27 (March 25)
- L28 (March 26)
- L29 (March 27)
Week 13: March 30, 2026
- L30 (April 1):
- L31 (April 2):
- April 3 - Good Friday
Week 14: April 6, 2026
- L32 (April 8) - Wednesday as Friday
- L33 (April 9)
- L34 (April 10)
Week 15: April 13, 2026
- L35 (April 15)
- L36 (April 16)
- L37 (April 17)
Week 16: April 20, 2026
- L38 (April 22)
- L39 (April 23)
- L40 (April 24)
Week 17: April 27, 2026
- L41 (April 29)
- L42 (April 30)
Week 18: May 5, 2026
- End term exam (May 4 to May 13)

Grading scheme

Mid term (30%)
End term (30%)
Lab and project (30%)
- N-1 lab tests: 15% (typical value of N is 4)
- 15% project.
Class-participation/In-class Quizzes (10%)
- 80% of in-class quizzes will be considered for evaluation. Each in-class activity would account for 1 point. If total activities were 40, then maximum marks in class participation would be 32 which in tern would be scaled to 10 points.

General guidelines:

All the submissions should be on time. Delayed submission will attract penalty at the rate of 10% per day. After delay of 10 days, no marks will be given to a assignment.
During lab test, every five minute of delay will attract penalty at the rate of 10% per day.
Plagiarism of any sort (from internet resource or from friends) will be heavily penalised. In case, the case of copy is from other students of the course, both parties will get negative marks equal to double the weightage of assignment/submission. In second instance (across your studentship at IIT Ropar) will be given F.

Books

Text Books

Computer Organization and Design RISC-V Edition: The Hardware Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design) by David A. Patterson (Author), John L. Hennessy (Author)
Basic Computer Architecture, Version 2.1 by Smruti R. Sarangi
Computer Systems – A programmer's perspective by R. E. Bryant and D. R. O’Hallaron, Pearson publisher, 3rd edition

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