15.2 Flip-Flops
Specification
show understanding of how to construct a flip-flop (SR and JK)
draw a logic circuit and derive a truth table for a flip-flop
understand the role of flip-flops as data storage elements
NOTE
This can quickly become a very confusing and challenging topic...if you let it. For the exam, you should be able to draw the SR (NAND/NOR) and J-K circuits and their respective truth-tables. You also need to know their use as a primitive type of memory (other types of memory such as D-RAM use capacitors)
Sequential and Combinational Circuits
In digital circuit theory:
sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on the previous input, the input history through simple memory.
Combinational logic circuitry's output is a function of only the present input and is what you have studied up until this point..
Latches and Flip-flops
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are fundamental building blocks of digital electronics systems used in computers, communications, and many other types of systems.
Flip-flops and latches are used as data storage elements. A flip-flop stores a single bit (binary digit) of data; one of its two states represents a "one" and the other represents a "zero".
Data Storage
A flip flop stores one bit at a time in digital circuit. In order to store more than one bit, flip flops can be connected in both series and parallel combinations called registers. A register is simply a data storage device for a number of bits in which each flip flop store one bit of information (0 or 1). Thus a 4 bit register consists of 4 individual flip flops, each able to store one bit of information at a time.
Data Transfer
Flip flops can be used extensively to transfer data. For this purpose, a shift register is used. A shift register is a register which is able to shift or transfer its content within itself without changing the order of the bits. It may be designed to shift or transfer data either left or right. The data is shifted or transferred one bit at a time, when a clock pulse is applied. The shift register can be used for temporary storage of data. A shift register is used for multiplication and division where bit shifting is required. The shift register can be built using RS, JK or D flip flops (not covered in specification).
Tracing Sequential Circuits
The lesson gives an animated example of how to trace. But simply:
Set up your inputs for what you are tracing
Set an initial state of the top gate (0 or 1)
Now check the bottom gate with the two inputs
Given the bottom state, now run through the top state
You can repeat steps 3 and 4 until the internal state is stable
SR Vs JK Flip-Flop
In their most basic form, flip-flops are nothing but a combination of logic gates so arranged that it renders an element of memory to the arrangement.
A simple SR flip flop is one where there is no clock (all JK flip flops are clock driven). There are two ways of creating SR flip flops by using NOR or NAND gates. Why? Because the NAND version uses a low state (0) to drive the outputs. E.g. With S (Set) =0 and R (Reset) =1 Q is set high (1) and Q^ set low (0). This section has been updated following the W22 QP32 mark scheme. It goes against some sources, but CAIE seemingly will allow you to pick one method if requiring you to draw the circuit.
Both NAND and NOR have been used by CIE in exams.
SR flip-flop is a set reset flip flop whose outputs Q and Q’ are 1 or 0 depending upon the inputs S and R. One distinct state of this flip flop is the condition when both S and R are 0s (NAND configuration) OR 1 (NOR). In that condition both Q and Q’ tend to become 1 which is logically incoherent. Thus this state is considered an invalid state. A J-K does not have this problem.
This diagram was updated since the Winter '22 (QP32) paper's markscheme
With a NOR configuration, the table is reversed in that inputs of 1 cause an invalid state, etc. The NAND version explains how to read the states if you are unable to memorise the truth tables for each.
JK Truth Table
Coming to the JK flip flop, there are two special states of this flip flop, one is when both inputs are 0s. In this condition the output does not change state and stores the last value. Another is where both inputs are 1s. In this state the final output is the complement of whatever was the last state of the output. One thing necessary for this is that the JK flip flop must be edge triggered. Else what happens is that in a single clock pulse, the output keeps changing state continuously. JK flip-flops always require a clock pulse to stabilise the inputs.
Metastability is a property which can occur by inputs triggering at the same time, causing uncertainty over which was first, etc. JK flip-flops avoid this by ensuring it is edge triggered.
The JK flip-flop is a universal flip-flop, because it can be configured to work as an SR flip-flop, a D flip-flop, or a T flip-flop.
The Set State
Consider the circuit shown above. If the input R is at logic level “0” (R = 0) and input S is at logic level “1” (S = 1), the NAND gate Y has at least one of its inputs at logic “0” therefore, its output Q must be at a logic level “1” (NAND Gate principles). Output Q is also fed back to input “A” and so both inputs to NAND gate X are at logic level “1”, and therefore its output Q must be at logic level “0”.
Again NAND gate principals. If the reset input R changes state, and goes HIGH to logic “1” with S remaining HIGH also at logic level “1”, NAND gate Y inputs are now R = “1” and B = “0”. Since one of its inputs is still at logic level “0” the output at Q still remains HIGH at logic level “1” and there is no change of state. Therefore, the flip-flop circuit is said to be “Latched” or “Set” with Q = “1” and Q = “0”.
Reset State
In this second stable state, Q is at logic level “0”, (not Q = “0”) its inverse output at Q is at logic level “1”, (Q = “1”), and is given by R = “1” and S = “0”. As gate X has one of its inputs at logic “0” its output Q must equal logic level “1” (again NAND gate principles). Output Q is fed back to input “B”, so both inputs to NAND gate Y are at logic “1”, therefore, Q = “0”.
If the set input, S now changes state to logic “1” with input R remaining at logic “1”, output Q still remains LOW at logic level “0” and there is no change of state. Therefore, the flip-flop circuits “Reset” state has also been latched and we can define this “set/reset” action in the following truth table.
Videos
The videos below give a good introduction to the topic and explain different types of flip-flop. D types are mentioned, but the specification only mentions SR and JK. See above for how JK differs from SR flip-flops. I have therefore cut out some of the videos in his series on flip flops.
Links
The following websites describe these in more detail, but also give detail on additional flip-flop types and other electrical engineering content that is not necessary.