CISC and RISC

• show understanding of the differences between RISC and CISC processors

• show understanding of the importance/use of pipelining and registers in RISC processors

• show understanding of interrupt handling on CISC and RISC processors

A very good resource which covers this section well, can be found here.

Control Unit

The control unit handles the fetching, decoding and executing of instructions. It is not the control unit that does the work, but ensures that each instruction is handled correctly with the different parts enacted when needed (e.g. ALU, registers, etc.). While this does not feature explicitly in the specification, it is included to give some wider understanding of the processes used by CPUs.

Hard-Wired

In a hard-wired control unit, the term relates to the physical logic components (sequential logic units) that enable instructions to be processed. The instructions are encoded pathways for the different bits to be sent to the relevant set of transistors which will process the data. Hardwired control units are generally faster than microprogrammed designs.

Their design uses a fixed architecture—it requires changes in the wiring if the instruction set is modified or changed. This architecture is preferred in reduced instruction set computers (RISC) as they use a simpler instruction set.

The hardwired approach has become less popular as computers have evolved.

Microprogrammed

In a microprogrammed control unit (CU), the pathways for enabling instructions (the control signals) are soft-wired. E.g. they are directed via software (stored in the CU) and the various actions taking place during a typical instruction fetch are programmed.

Processor type

There are two main types of CPU: CISC and RISC.

RISC, or Reduced Instruction Set Computer is a type of microprocessor architecture that utilises a small, highly-optimised set of instructions, rather than a more specialised set of instructions often found in other types of architectures such as CISC. RISC does not actually refer to the number of instructions, but the complexity of each. Being that a single instruction can be completed in one clock cycle.

Most desktop or laptop computers use CISC (complex instruction set computing) architecture made by Intel or AMD. Smartphones and tablets use RISC ARM architecture.

The key differences between the two architectures are:

• • Instructions - RISC has generally fewer instructions than CISC. CISC generally have hundreds of instructions whereas RISC usually has a lot less. To do complex tasks, RISC CPUs must combine simple operations from their reduced instruction set. The instruction cycle in CISC is more complex than RISC, so RISC can be more efficient at performing simpler tasks.

  • Physical size - in order to handle all those instructions CISC CPUs are larger and require more silicon to make.

  • Speed - RISC CPUs run at a lower clock speed than CISC CPUs. They can perform simpler tasks more quickly than CISC, but more intensive tasks will be better on a CISC CPU. However, smartphones and tablets are generally not used to do intensive tasks like playing the most hi-spec advanced games.

  • Energy consumption - because CISC CPUs are larger, they use more electricity. RISC CPUs are designed to use less power and they can go into 'sleep mode' when not actively processing a program.

  • Design - smartphones and tablets combine their processing architecture into a system on a chip (SOC). As RISC CPUs are much smaller than CISC, more functions (including the memory and other hardware) can be combined with the CPU in one chip. CISC CPUs are usually built into a system which has a heat sink and fan to cool them down. Smartphones or tablets do not have space for heat sinks or fans.

  • Cost - RISC CPUs use less power and are cheaper to make.

The following table summarises these points:

Important notes:

CISC allows for many types of memory addressing not found in RISC. Again, this was through design as RISC. RISC makes extensive use of registers, specifically general purpose registers.

Also, because there are advantages to using RISC, modern day CISC architectures are more of a hybrid, allowing for RISC based instructions and power usage.

Memory Usage

CPUs process data using instructions stored in the computer memory or RAM. The RAM is a temporary storage area that makes information and instructions available to the microprocessor, which does not have to use this information until required. The two processor classifications are the Reduced Instruction Set Computer (RISC) and the Complex Instruction Set Computer (CISC). The primary difference between the two is that a RISC-based chip uses more basic instruction sets to achieve a greater clock frequency to process more information per clock cycle than a CISC processor. CISC-based chips, however, give developers the ability to do more with a shorter program due to the greater library of complex instructions embedded in the CISC chip.

Storage and Ram are still more expensive then the processor itself, RISC was made popular because due to the explosion of iPhone and Android devices. However, the most complex and functional Apps on iOS and Android are still rather limited, and it's not just because of touch, but because RISC systems are designed to run small and simple programs, the larger and complex the programs get, the more RISC suffers because it will eat up expensive storage and RAM. Due to the limited number of instructions, programs for RISC are much bigger and are unable to handle heavy processing, which was not the initial intention of RISC. CISC programs are much smaller because the processor offers a single instruction that may take 5 or 6 instructions (or more) to achieve on RISC. Also, due to this, optimisation of code is a more significant factor than in CISC.

A common debate that arises is which type of processor is the better one to use.

Processor architecture: CISC Vs RISC

When it comes to the architecture of a CPU, modern day chips are a hybrid of these two different methodologies. The videos at the end give a good description, but you'll also find a good summary when viewing the videos in 3.4.3 compilers.

CISC

A computer microprocessor that is based on CISC architecture has many instructions built into the chip. This makes the processing time for work more efficient since the required instructions are available directly to the microprocessor and do not have to be loaded from the computer’s memory or RAM. Although the CISC architecture helps speed up the programs’ execution, the number of instructions loaded on the processor negatively impacts processor performance. As a result, more transistors are built into the microprocessor to improve performance, which can result in an increase in the unit’s cost. CISC processors are most commonly used in personal computers (PCs).

RISC

The RISC architecture was developed to address the CISC processors’ issues. They have limited instruction sets built into the processor, resulting in fewer transistors having to be used in processor construction. This saves space on the microprocessor and results in a lower overall cost for the unit. To do work that is equivalent to what a CISC processor can do, a greater amount of computer RAM or memory is required. RISC processors were initially favoured for scientific purposes since these applications did not require as large of an instruction set as general purpose computers. In recent years, however, an increasing number of general purpose PCs using RISC microprocessors have been produced.

Pipelining and Registers

Pipelining is a feature whereby the processor is able to simultaneously execute parts (stages) of instructions to allow more efficient processing.

RISC architectures lend themselves more towards pipelining than CISC architectures for many reasons. As RISC architectures have a smaller set of instructions than CISC architectures in a pipeline architecture the time required to fetch and decode for CISC architectures is unpredictable.

CISC architectures by their very name also have more complex instructions with complex addressing modes. This makes the whole cycle of processing an instruction more complex. Pipelining requires that the whole fetch to execute cycle can be split into stages where each stage does not interfere with the next and each instruction can be doing something at each stage. RISC architectures because of their simplicity and small set of instructions are simple to split into stages. CISC with more complex instructions are harder to split into stages. Stages that are important for one instruction may be not be required for another instruction with CISC.

The remaining section will focus on RISC pipelining as this is covered in the specification.

Classic Fetch-Execute stages in RISC

The classic 5 stages which contribute to the RISC pipeline are: IF, ID, EX, MEM, WB. Assuming a 32-bit processor is being used, each stage works as follows:

Instruction fetch (IF)

The Instruction Cache on these machines had a latency of one cycle, meaning that if the instruction was in the cache, it would be ready on the next clock cycle. During the Instruction Fetch stage, a 32-bit instruction is fetched from the cache.

The Program Counter, or PC, is a register that holds the address of the current instruction. It feeds into the PC predictor, which then sends the Program Counter (PC) to the Instruction Cache to read the current instruction.

Instruction decode (ID)

Figure out what the instruction says to do:

• • Get values from the named registers

  • Simple instruction format means we know which registers we may need before the instruction is fully decoded

Execute (EX)

The Execute stage is where the actual computation occurs. Typically this stage consists of an Arithmetic and Logic Unit, and also a bit shifter.

The Arithmetic and Logic Unit is responsible for performing Boolean operations (and, or, not, nand, nor, xor, xnor) and also for performing integer addition and subtraction. Besides the result, the ALU typically provides status bits such as whether or not the result was 0, or if an overflow occurred.

The bit shifter is responsible for shift and rotations.

Memory access (MA)

• • If load or store, access memory

  • If branch, replace PC with destination address

  • Otherwise do nothing

Writeback (WB)

During this stage instructions write their results into the appropriate register.

In a RISC machine most of the instruction will be performed on registers and memory is addressed only in index mode.

The diagram above shows how pipelining can be used to execute multiple stages of instructions simultaneously. The diagram is showing that the instruction started in clock cycle 1 is in its 5th stage, while the second instruction (started in the 2nd cycle) is in the 4th stage, etc. The cycle is shown more clearly below.

As you can see, the 5th instruction would be complete on the 9th clock cycle. Without pipelining, the 5 instructions would require 25 clock cycles, giving a saving of 16 clock cycles through use of pipelining.

Pipeline Problems

Pipelining can bring some problems. For example, a data dependency occurs when an instruction depends on the results of a previous instruction. A particular instruction might need data in a register which has not yet been stored since that is the job of a preceding instruction which has not yet reached that step in the pipeline.

For example:

ADD $r3, $r2, $r1

ADD $r5, $r4, $r3

more instructions that are independent of the first two

In this example, the first instruction tells the processor to add the contents of registers r1 and r2 and store the result in register r3. The second instructs it to add r3 and r4 and store the sum in r5. We place this set of instructions in a pipeline. When the second instruction is in the second stage, the processor will be attempting to read r3 and r4 from the registers. Remember, though, that the first instruction is just one step ahead of the second, so the contents of r1 and r2 are being added, but the result has not yet been written into register r3. The second instruction therefore cannot read from the register r3 because it hasn't been written yet and must wait until the data it needs is stored. Consequently, the pipeline is stalled and a number of empty instructions (known as bubbles go into the pipeline. Data dependency affects long pipelines more than shorter ones since it takes a longer period of time for an instruction to reach the final register-writing stage of a long pipeline.

A more modern solution (MIPS' architecture) to this problem is code reordering. If, as in the example above, the following instructions have nothing to do with the first two, the code could be rearranged so that those instructions are executed in between the two dependent instructions and the pipeline could flow efficiently. The task of code reordering is generally left to the compiler, which recognises data dependencies and attempts to minimise performance stalls.

Interrupt Handling

As discussed in Section 1, interrupts are a way of getting the processor's attention when needed. Interrupts can be software or hardware initiated and after each FE cycle, the interrupt register is checked. Interrupts are given priorities and these are discussed in the next section under operating systems.

While interrupts can be a simple process for single instructions, where you have multiple instructions at different stages, decisions have to be taken.

One option is to flush all but the first instruction from the pipeline and then process the interrupt. Another option is to construct individual program counters for each stage, thereby, enabling the entire state of the CPU to be stored before enacting the interrupt service routine (ISR).

Videos

A not so useful video, which some pupils seem to find somewhat helpful (I have no idea why!)

Summary

RISC (Reduced Instruction Set Computer)

RISC stands for Reduced Instruction Set Computer. To execute each instruction, if there is separate electronic circuitry in the control unit, which produces all the necessary signals, this approach of the design of the control section of the processor is called RISC design. It is also called hard-wired approach.

CISC (Complex Instruction Set Computer)

CISC stands for Complex Instruction Set Computer. If the control unit contains a number of micro-electronic circuitry to generate a set of control signals and each micro-circuitry is activated by a micro-code, this design approach is called CISC design. http://www.eazynotes.com/pages/computer-system-architecture/risc-and-cisc.html