This is a specialized course on Security aspects pertaining to Computer Architecture. And is open for all the students who have undertaken CS204: Computer Architecture or a similar course. The course will dive into many topics pertaining to the current state-of-the art security vulnerabilities at microarchitecture and memory. The required basics would be revised.

As progress in technology scaling as been hampered by the physical limitations, an abundant number of complex techniques and optimizations have been introduced to keep improving performance with power consumption in check. Off late, many microarchitectural attacks have been proposed that leak a lot of sensitive data using components like branch predictors, caches, Translation look-aside buffers (TLBs), page tables, prefetchers, Network-on-Chip (NoC), Dynamic Random Access Memory (DRAM) controllers, DRAM, and non-volatile memories (NVMs).

This course aims to make students understand:

1. How these components are prone to timing-, side- and covert-channel attacks, denial-of-service, wear-out attacks, becoming sources of information leakage and/or affecting performance and power.

2. How to understand and break these attacks.

3. Analyze defensive mechanisms against these attacks with a tab on performance and power.

1. Module 0: Introduction

   • Motivation and current state of various hardware attacks 

2. Module 1: Microarchitectural attacks

   • 1.1 Brief review of modern processors - Revise the design concepts of a typical modern day processor – multithreading, speculation, multicores

   • 1.2 Study Spectre, Meltdown, Voltage/frequency scaling based attacks, Branch prediction and value prediction based attacks, power side channel attacks

3. Module 2: Memory based attacks

   • 2.1 Brief review of modern memory hierarchy - Revise Cache, main memory, secondary memory, virtual memory concepts. Prefetching

   • 2.2 Side-, timing-, covert-channel attacks on Caches, memory, TLB, etc. 

4. Module 3: Network-on-Chip and Storage based attacks

   • Network-on-chip related attacks because of malicious implants/backdoor testing interfaces, other vulnerabilities 

   • Study of attacks like Ransomeware, secure erasure, encryption, etc 

*Few changes in the content and flow can be expected.

1. Contents of the course will be primarily from fundamental/high-impact research papers.

2. Jakub Szefer, Principles of Secure Processor Architecture Design, Morgan & Claypool Publishers

Reference books:

1. Computer Architecture: A Quantitative Approach by David A Patterson, John L Hennessy, 5th edition.

2. Memory Systems: Cache, DRAM, Disk by Bruce Jacob, Spencer Ng and David Wang, 2007.

3. Books from Synthesis Lectures on Computer Architecture

• This section will be updated soon, but will surely contain:

  • Paper reading assignments

  • Term paper submission

• This course falls in PEOE slot.

• Class timings: 

  • Tue 03:00PM - 03:50PM

  • Thu & Fri 12:00Noon - 12:50PM

• Venue: CS - Seminar Hall, S Ramanujan Block

• All the lecture material will be shared on the Classroom