Legend - G: Grant/Issue, F: File, P: Publish
G10: Anshuman Khandual, Saravanan Sethuraman, Venkata Kalyan Tavva and Anand Haridass. Method to Efficiently Map Memory Allocation Requests Using Memory Attributes. US Patent Number US11307796, 19th Apr 2022.
G9: Saravanan Sethuraman, Karthick Rajamani, Venkata Kalyan Tavva, Hillery Hunter, Chitra K Subramanian and Kyu-hyoun Kim. Method and system to improve read reliability in memory devices. US Patent Number US11074968, 27th July 2021.
G8: Dharmesh Parikh, Stephen J Powell and Venkata Kalyan Tavva. DRAM Bank Activation Management. US Patent Number US11042312, 22nd June 2021.
G7: Saravanan Sethuraman, Venkata Kalyan Tavva, Adam McPadden and Hillery Hunter. Write management for increasing non-volatile memory reliability. US Patent Number: US10949122, 16th Mar 2021.
G6: Srinivas Purushotham, Naveen M and Venkata Kalyan Tavva. Scope Resolution Tag Buffer to Reduce Cache Miss Latency. US Patent number: US10831659, 10th Nov 2020.
G5: Anshuman Khandual, Archana Ravinder, Saravanan Sethuraman and Venkata Kalyan Tavva. Predicting Physical Memory Attributes by Compiler Analysis of Code Blocks. US Patent Number US10802809, 13th Oct 2020.
G4: Stephen J Powell, Venkata Kalyan Tavva and Dharmesh Parikh. DRAM Bank Activation Management. US Patent, filed 2017. US Patent Number US10572168, 25th Feb 2020.
G3: Venkata Kalyan Tavva, Dharmesh Parikh and Stephen J Powell. Memory Request Scheduling To Improve Bank Group Utilization. US Patent Number US10380040 B2, 13th August 2019.
G2: Saravanan Sethuraman, Venkata Kalyan Tavva, Adam McPadden and Hillery Hunter. Write management for increasing non-volatile memory reliability. US Patent Number US10379784B1, 13th August 2019.
G1: Venkata Kalyan Tavva. Per Die Based DRAM Refresh Control Based on a Master Controller in a Hybrid Memory Cube. US Patent Number US9734887 B1, 15th August 2017.
P: Venkata Kalyan Tavva, Saravanan Sethuraman, Hillery Hunter, Michael Healy and Diyanesh Chinnakkonda. Method and Apparatus to improve thermal challenges in 3D-Stacked DRAM. Defensive Publication in https://www.ip.com/, 2016.
Note: The sequence of the list of inventors in a Patent is not necessarily a representation of their actual contribution. Worldwide, many different naming conventions are followed.
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