International Journals 

International Journals (40)

1. J. Ha, J. Kim* et al., "Abnormal Operation of 6-T SRAM based on Nanosheet FET due to Total Ionizing Dose" in IEEE Access, Sep. 2025. (Accepted)

2. M. Ryu, J. Kim* et al., "Single-Event Upset and Total Ionizing Dose Effects on DDR4 DRAM Due to Proton Irradiation Under Different Temperatures" in IEEE Transactions on Electron Devices, Aug. 2025.

3. M. Ryu, J. Kim* et al., "Soft Error in Saddle Fin-Based DRAM at Cryogenic Temperature" in IEEE Access, Jul. 2025.

4. D. Lee, J. Kim* et al., "Investigation of TID and DD Effects on FD SOI Nanowire FET Induced by Proton Irradiation" in IEEE Transactions on Electron Devices, Apr. 2025.

5. M. Suh, J. Kim* et al., "Comprehensive Hammering and Parasitic BJT Effects in Vertically Stacked DRAM," in IEEE Access, October. 2024. (Early access)

6. M. Bang, J. Kim* et al., "Mitigation of Single Event Upset Effects in Nanosheet FET 6T SRAM Cell," in IEEE Access, vol. 12, pp. 130347-130355, September. 2024.

7. H. Bae, G. Lee, J. Yoo, K. Lee, J. Ku, K. Kim, J. Kim, Peide D. Ye, J. Park, Y. Choi, “Low-frequency noise characterization of positive bias stress effect on the spatial distribution of trap in β-Ga2O3 FinFET,” Solid-State Electronics, May. 2024.

8. M. Suh, M. Ryu, J. Ha, M. Bang, D. Lee and J. Kim*, "Design Guideline of Saddle-Fin-Based DRAM for Mitigating Rowhammer Effect," in IEEE Transactions on Electron Devices, Feb. 2024

9. J. Ha, S. Kim, M. Bang, G. Lee, M. Suh, M. Shim, C. Kim, J. Kim*, “Prediction of Statistical Distribution on Nanosheet FET by Geometrical Variability Using Various Machine Learning Models.”, IEEE Access, Nov. 2023

10. G. Lee, M. Suh, M. Ryu, Y. Lee, J. -W. Han and J. Kim*, "Investigation Into the Degradation of DDR4 DRAM Owing to Total Ionizing Dose Effects", IEEE Access, Sep. 2023

11.  J. Ha, M. Bang, G. Lee, M. Suh, C. -E. Kim and J. Kim*, "Impact of Displacement Defect Owing to Cosmic Rays on Three-Nanometer-Node Nanosheet FET 6T Static Random Access Memory", IEEE Access, Sep. 2023

12.  J. -W. Han, M. Suh, G. Lee and J. Kim*, "Overhang Saddle Fin Sidewall Structure for Highly Reliable DRAM Operation", IEEE Access, Aug. 2023

13. M. Bang, J. Ha, G. Lee, M. Suh, J. Kim*, “Performance Degradation in Static Random Access Memory of 10 nm Node FinFET Owing to Displacement Defects”, Micromachines, May. 2023.

14.  J. Park, G. Yoon, D. Go, J. Kim*, and J.-S. Lee*, “Single Event Transient in 3D NAND Flash Memories”, IEEE Transactions on Electron Devices, Nov. 2022.

15.   I. Park, D. Lee, B. Jin, J. Kim, and J.-S. Lee*, “Effects of Carbon Incorporation on Electrical Characteristics and Thermal Stability of Ti/TiO 2/n-Ge MIS Contact ”, IEEE Access, Aug, 2022.

16.   J. Ha, G. Lee, K. Kim, H. Bae, J.-W. Kim, J. Kim*, "On-current Degradation of Nanosheet FET Owing to Displacement Defect by Cosmic Rays", Micromachines, Aug, 2022.

17.   G. Yoon, D. Go, J. Park, D. Kim, J. Kim, and J.-S. Lee, "Impact of P/E Stress on Trap Profiles in Bandgap-engineered Tunneling Oxide of 3D NAND Flash Memory", IEEE Access, June. 2022.

18.   G. Lee, J. Ha, K. Kim, H. Bae, C-E. Kim, J. Kim*, "Influence of Radiation-Induced Displacement Defect in 1.2 kV SiC Metal-Oxide-Semiconductor Field-Effect Transistors", Micromachines, June, 2022.

19.   I. Park, D. Lee, B. Jin, J. Kim, and J.-S. Lee*, “Improvement of Fermi-Level Pinning and Contact Resistivity in Ti/Ge Contact Using Carbon Implantation ”, Micromachines, Jan, 2022.

20.   J. Park, G. Yoon, D. Go, J. Kim*, and J.-S. Lee*, “Extraction of Nitride Trap Profile in 3-D NAND Flash Memory Using Intercell Program Pattern”, IEEE Access, Sep. 2021.

21.   J.-W. Han, J. Kim, and M. Meyyappan, "Total Ionizing Dose Effects on Nanosheet and Nanowire Field Effect Transistors", Microelectronics Reliability, Jun. 2021.

22.   J. Kim, S. J. Kim(co-first author), J.-W. Han*, and M. Meyyappan, "Machine Learning Approach for Prediction of Point Defect Effect in FinFET", IEEE Transactions on Device and Materials Reliability, Jun., 2021.

23.   S.-I. Yi, and J. Kim*, “Novel Program Scheme of Vertical NAND Flash Memory for Reduction of ZInterference”, Micromachines, May, 2021.

24.   K. Kim, and J. Kim *, "Insights into Radiation Displacement Defect in an Insulated-Gate Bipolar Transistor", AIP Advances, Feb. 2021.

25.   J.-W. Han*, J. Kim, D. Beery, K. D. Bozdag, P. Cuevas, A. Levi, I. Tain, K. Tran, A. J. Walker, P. Vadakupudhu, A. Arreghini, A. Furnemont, M. Meyyappan, “Surround Gate Transistor with Epitaxially Grown Si Pillar and Simulation Study on Soft Error and Row hammer Tolerance for DRAM”, IEEE Transactions on Electron Devices, Vol. 68, No. 2, Page. 529-534, Feb. 2021.

26.   J. Kim*, “The Impact of Displacement Defect in Nanosheet Field Effect Transistor", Journal of Electrical Engineering & Technology, Vol. 1, Page. 525-529, Jan. 2021.

27.   J.-W. Han*, M.-L. Seol, J. Kim, M. Meyyappan, “Nanoscale Complementary Vacuum Field Emission Transistor”, ACS Applied Nano Materials, Vol. 11, No. 3, Page. 11481-11488, Nov. 2020.

28.   J. Kim, J.-W. Han*, M. Meyyappan, “The Impact of a Single Displacement Defect on Tunneling Field-Effect Transistors”, IEEE Transactions on Electron Devices, Vol. 67, No. 11, Nov. 2020.

29.   J.-W. Han*, J. Kim, M. Meyyappan, “Transformable Junctionless Transistor (T-JLT)”, IEEE Transactions on Electron Devices, Vol. 67, No. 6, June. 2020.

30.   J. Kim, J.-S. Lee, J.-W. Han*, M. Meyyappan, “Caution: Abnormal Variability Due to Terrestrial Cosmic Rays in Scaled-Down FinFETs”, IEEE Transactions on Electron Devices, Vol. 66, No. 4, Apr. 2019.

31.   J.-W. Han*, J. Kim, J.-S. Lee, J.-W. Han, M. Meyyappan, “Soft Error in Saddle Fin Based DRAM”, IEEE Electron Device Letters, vol. 40, No. 4, Apr .2019.

32.   J. Kim, J.-S. Lee, J.-W. Han*, M. Meyyappan, “Single-Event Transient in FinFETs and Nanosheet FETs”, IEEE Electron Device Letters, Vol. 39, No. 12, Dec. 2018.

33.   J. Kim*, J.-W. Han, M. Meyyappan, "Reduction of Variability in Junctionless and Inversion-Mode FinFETs by Stringer Gate Structure", IEEE Transactions on Electron Devices, Vol. 65, No.2, pp.470-475, Feb. 2018.

34.   J. Kim, H. Oh, J. Kim, R.-H. Baek, J.-W. Han, M. Meyyappan, and J.-S. Lee*, “Work function consideration in vacuum field emission transistor design”, Journal of Vacuum Science Technology B. Vol. 35, pp.062203, Nov. 2017.

35.   J. Kim*, H. Oh, J. Kim, M. Meyyappan, and J.-S. Lee*, “Electrical Characteristics of Tunneling Field-Effect-Transistor (TFET) with Asymmetric Channel Thickness”, Japanese Journal of Applied Physics, 56, 024201, Jan. 2017.

36.   J. Kim, J. Kim, H. Oh, M. Meyyappan, J.-W. Han, and J.-S. Lee*, “Design Guideline for Nanoscale Vacuum Field Emission Transistors”, Journal of Vacuum Science Technology B. Vol. 34, pp.0422201, Mar., 2016.

37.   H. Oh, J. Kim, J. Lee, T. Rim, C.-K. Baek, and J.-S. Lee*, “Effects of Single Grain Boundary and Random Interface Traps on Electrical Variations of Sub-30 nm Polysilicon Nanowire Structures”, Microelectronic Engineering, vol.149, pp. 113-116, Jan. 2016.

38.   J. Kim, H. Oh, J. Lee, C.-K. Baek, M. Meyyappan, and J.-S. Lee*, “3D Simulation of Threshold Voltage Variations due to Oblique Single Grain Boundary in Poly-Silicon Nanowire FETs”, Semiconductor Science and Technology, Vol. 30, No.8, pp.08501, Aug. 2015.

39.   J.-S. Yoon, T. Rim, J. Kim, K. Kim, C.-K. Baek*, and Y.-H. Jeong, “Statistical variability study of random dopant fluctuation on gate-all-around inversion mode silicon nanowire field-effect transistors”, Applied Physics Letters, vol.106, pp.103507, Mar. 2015.

40.   B. Jin*, J. Kim, D.-H. Pi, H. S. Kim, M. Meyyappan, and J.-S. Lee, "Role of an encapsulating layer for improved resistance drift in phase change random access memory," AIP Advances, vol. 4, no. 12, pp. 127155, Dec. 2014.

41.   J.-S. Yoon, T. Rim, J. Kim, M. Meyyappan, C.-K. Baek*, and Y.-H. Jeong, “Vertical gate-all-around junctionless nanowire transistors with asymmetric diameters and underlap lengths”, Applied Physics Letters, vol.105, pp.102105, Sep. 2014.

42.   J. Kim, T. Rim, J. Lee, C.-K. Baek, M. Meyyappan, and J.-S. Lee*, “Threshold Voltage Variations due to Oblique Single Grain Boundary in Sub- 50 nm Poly-Silicon channel”, IEEE Transactions on Electron Devices, Vol. 61, No.8, pp.2705, Aug. 2014.

43.   B. Jin, D. Kang, J. Kim, M. Meyyappan, and J.-S. Lee*, "Thermally Efficient and Highly Scalable In2Se3 Nanowire Phase Change Memory", Journal of Applied Physics, vol. 113, no. 16, pp. 164303, Apr. 2013.

44.   C.-K. Baek, D. Kang, J. Kim, B. Jin, T. Rim, Sooyoung Park, Y.-H. Jeong, M. Meyyappan, and J.-S. Lee*, "Improved performance of In2Se3 nanowire phase-change memory with SiO2 passivation" , Solid State Electronics, vol.80, pp. 10, Feb. 2013