Clock Generation Integrated Circuit Design

An important motive of phase-locked loop (PLL) usage is to generate an accurate and low noise clock signal with programmable frequency on chip. Since almost all the integrated systems operate by an intended accurate clock signal (normally in high frequency band) the PLL is a very crucial in modern IC systems. A clock signal from on-chip free running voltage-controlled oscillator (VCO) is quite clean (low phase noise), but its center frequency is sensitive to PVT variation and can drift for a long time without a loop. An off-chip crystal oscillator can create an accurate and intended frequency but normally its center frequency is low, so people have built a negative feedback loop to force the frequency of VCO clock signal (fvco) to become N times the frequency of crystal oscillator clock signal (fref), where N is a dividing ratio between fdiv and fvco. When the two phases between CKref (A) and CKdiv (B) are aligned, the fdiv approaches to fref and fvco is locked to N x fref where both N and fref are accurate values. Now, the VCO clock frequency fvco become accurate, which has already low phase noise characteristic, and CKvco can be used to trigger any on-chip synchronous digital system with high frequency, high accuracy and low phse noise. If the dividing ratio N is controlled digitally and the VCO is designed with a wide frequency tunning range, the VCO with a negative feedback loop (PLL) can generate an clock signal with accurate and programmable frequencies (various N x fref values). This is called "clock synthesis", a very important function of PLL system. 

There are many challenging issues to design a PLL with high performances. The high frequency VCO and divider pre-scaler burn huge power. The overall chip size is large due to the integrating capacitor and passive devices used in loop filter and oscillator. Many noise sources like inband noise, variation of dividing ratio for fractional and dithering function, oscillator flicker noise and supply noise coupling, easily translate to jitter at the output of VCO. It is very hard to conduct noise trade-off. Lastly but not leastly, many blocks are in analog circuit format, so difficult to be automated.

On the other hand, a ring VCO (shown in the top right corner) can be designed with low chip area. The mechanism to raise and maintain oscillation condition is different from the LC VCO case. Once a noisy signal occurs in the loop, it goes around the loop infinitely and the overall phase noise performance is inferior to the LC VCO's. In addition, the output swing varies while tuning the frequency, so a scheme to control the frequency and maintain a constant swing as shown on the bottom left corner needs to be applied. In modern digital PLLs, a digital Vctrl[N-1:0] code controls the output frequency of the oscillator rather than analog voltage Vctrl(V) does. A digitally-controlled oscillator (DCO) is nothing but DAC plus VCO. It is important to design the DCO with low Kdco to suppress quantization noise.

A demand for reducing flicker noise in VCO continuously increases every year because VCO noise decides envelope of overall PLL noise. Removing the current source is useful to suppress the flicker noise but CMRR degrades. Designing an oscillator having a low phase noise, low power, wide tuning range and low area is a good and important research topic for circuit designers. 

An analog charge pump-based PLL on the left hand side figure, normally consumes large chip area because the size of C1 becomes huge for the PLL to have a proper loop bandwidth and phase margin. Addtionally charge pump, loop filter, oscillator and high-speed current-mode logic divider are in analog domain and hand crafted, which requires engineer's labor. Research motivation of digital PLL is low area performance by replacing the integrating capacitor C1 with low area digital loop filter Ki/1-z^-1, as shown on the right hand side figure. Since the signals of input and output of the filter is in a digital bus format, the phase detecter at the output should produce a digital signal (Btdc[n]) and the VCO frequency should be controlled by a digital bus (Bctrl[n]). The former detecter is called time-to-digital converter (TDC), in which the digital code Btdc[n] is proportional to the phase difference at the input. The latter oscillator is called digitally-controlled oscillator (DCO). Since a digital portion of overall PLL system increases, the performance of PLL benefits from advantage of shrinking technology - high speed, low area, low power, easy to be automated (portability from process to process). The signal of each node is absolutely linear because of digital signalling nature. 

However, one big disadvantage is a phase noise performance. The quantization error of TDC is a large inband noise source to overcome in presence of  oscillator flicker noise trade-off. The issue casts the need for a high resolution performance on TDC, which can be normally achieved by burning lots of power and by sophisticated calibration back-end to linearize the phase difference to the code relation. For the last decade many brilliant ideas to improve the resolution and power performances of TDC have been devised, but still more ideas to improve the TDC performance have been coming out every year.