Chip Gallery
4.8 Gbit/s x 4 Channel Differential pre/post FIR I/O and CDR Design
10 ~ 12 GHz Digitally-Controlled Oscillators and Phase Rotators Design
5.4 Gbit/s Display Port IO Transceiver Design
4.8 GHz Fractional Phase-Locked Loop Design
4 Gbit/s x 4 Lanes LPDDR4 Standard IO Transceiver Design
12.5 Gbit/s x 2 Channel UHDTV High-Speed IO Transceiver Design
1~16 Gbit/s Continuous-Rate Adaptive IO Transceiver Design for On-Chip Interface
Pseudo-Reference Counter-Based FLL for 6 Gbps Reference-less CDR
4.6 GHz Type-I-Like Low Noise Digital Phase-Locked Loop (1800 um x 1000 um)