Principal Investigator
Taehyoun Oh
Professor at Department of Electronic Engineering in Kwangwoon University
Research Interests
• Clock Generation / Timing Recovery Circuits
‒ Analog/Digital Phase Lock Loop Systems
‒ High-Speed Clock Recovery Loop Systems
• IO transceiver circuits
‒ IO Transmitters / Continuous-Time Linear Equalizers / Decision Feedback Equalizers
‒ Adaptive Equalization Loop Algorithms
‒ Crosstalk Noise Cancelling I/O Architectures
Education
• Ph.D. ECE University of Minnesota, Twin-Cities (2008.9 - 2012.7)
• MS. EE Seoul National University (2005.3 - 2007.2)
• BS. EE Seoul National University (1998.3 - 2005.2)
Career
• Asistant Professor at Kwangwoon University, Department of Electronic Engineering, Seoul (2013.3 - current)
• Advisory Engineer at High-Speed Sedes Group IBM, Fishkill, NY (2012.7 - 2013.2)
• Ph.D. Intern at Intel, Santa-Clara, CA (2011.7 - 2012.1)
• Ph.D. Intern at AMD, Boston Design Center, MA (2010.6 - 2010.9)
• Analog Circuit Designer, at Radiopulse, Seoul (2007.6 - 2008.5)
Honors and Awards
• Best Paper Award in analog circuit session in SRC TECHCON, Tx (2012.9)
• Travel Grant Award in VLSI Circuit Symposia, Hi (2012.6)
• Best Paper Award in analog circuit session in SRC TECHCON, Tx (2011.9)