Publications

[1] A 5Gb/s 2×2 MIMO Crosstalk Cancellation Scheme for High-Speed I/Os

Taehyoun Oh and Ramesh Harjani, IEEE Custom Integrated Circuits Conference, Sept 2010

[2] A 6 Gb/s MIMO Crosstalk Cancellation Scheme for High-Speed I/Os

Taehyoun Oh and Ramesh Harjani, (invited)  IEEE Journal of Solid-State Circuits, August  2011

[3] A 10 Gb/s MIMO Channel Equalization and Crosstalk Cancellation Architecture for High-Speed I/Os

Taehyoun Oh and Ramesh Harjani, TECHCON, September 2011

[4] 4x12 Gb/s 0.96 pJ/b/lane Analog-IIR Crosstalk Cancellation and Reutilization Receiver for Single-Ended I/Os in 65 nm CMOS

Taehyoun Oh and Ramesh Harjani, IEEE VLSI Circuits Symposium, June 2012

[5] Adaptive Calibration Algorithm for MIMO Channel Equalization and Crosstalk Cancellation

Taehyoun Oh and Ramesh Harjani, TECHCON, September 2012

[6] A 12Gb/s Multi-Channel I/O using MIMO Crosstalk Cancellation and Signal Reutilization in 65nm CMOS

Taehyoun Oh and Ramesh Harjani, IEEE Journal of Solid-State Circuits, Vol 48, No. 6, June 2013

[7] A 4 Gb/s, 370 uA low-power Tx FIR driver for LPDDR4 applications

Taehyoun Oh, Myung Chul Park, and Yun Seong Eo, IEICE Electronics Express, Vol. 11 (2014) No. 5 pp. 20130825

[8] Adaptive Techniques for Joint Optimization of XTC, AGC and DFE Loop Gain in High-Speed I/O

Taehyoun Oh and Ramesh Harjani, ETRI journal, 2015

[9] A 4.1 mA Adaptive Duty-cycle Corrector Loop with Background Calibration in 45 nm CMOS Process

Esther Kim, Deokgwan Jeong and Taehyoun Oh, ISOCC, 2016

[10] Single-ended 2 ch. x 3.4 Gb/s Dual-mode Near-ground Transmitter IO Driver in 45 nm CMOS Process

Esther Kim and Taehyoun Oh, IET Electronics Letters, 2017

[11] A 2-8 GHz Adaptive Duty-Cycle Corrector Loop with Background Calibration

Esther Kim, Youngjoo Lee and Taehyoun Oh, IET International Journal of Electronics, 2017

[12] Mismatch-Tolerant Capacitor Array Structure for Junction-Splitting SAR Analog-to-Digital Conversion

In-Cheol Park, Taehyoun Oh and Youngjoo Lee, IEIE Journal of Semiconductor Technology and Science, 2017

[13] 2 x 3.2 Gbps Single-Ended IO Transmitter with Low-Power Dynamic FIR Driver for the LPDDR4 Standard

Seongkwang Kim and Taehyoun Oh, IET Electronics Letters, 2017

[14] 0.5-4.4 Gbps PAM4/NRZ Dual-mode Transceiver with 0.6 V Near-Ground NMOS Driver for Low-Power Memory Interface

Kyunghwan Min and Taehyoun Oh, IET Electronics Letters, 2018

[15] A 0.18 um CMOS UWB Transceiver with a Backend SoC for Wireless Body Area Network Applications

Myung Cheol Park, Won Il Chang, Dong-Sun Kim, Tae-Ho Hwang, Taehyoun Oh and Yun Seong Eo, IEEE Transactions on Microwave Theory and Techniques, 2018

[16] 12 Gbit/s 3-Tap FFE Half-Rate Transmitter with Low Jitter Clock Buffering Scheme

Kyungseok Park and Taehyoun Oh, IET Electronics Letters, 2019

[17] High-Speed Clock and Data Recovery System with Segmented Slew-Rate Control Circuit for High-Linearity in 65 nm CMOS Process

Kyunghwan Min, Sanggeun Lee and Taehyoun Oh, IEIE Journal of Semiconductor Technology and Science 2021

[18] 12.2 GHz All-Digital PLL with Pattern Memorizing Cells for Low Power/Low Jitter using 65 nm CMOS Process

Sanggeun Lee and Taehyoun Oh,  IEIE Journal of Semiconductor Technology and Science 2021

[19] Linear Characteristic Analysis of High-Resolution Counter-Based Frequency Dector in Type-I Digital PLL

Taehyoun Oh, Joonho Gil and Ramesh Harjani, IEEE Transactions on Circuits and Systems-II, Express Briefs, 2022

[20] Pseudo-Reference Counter-Based Frequency-Locked Loop for 6 Gb/s Reference-Less CDR in 65 nm CMOS

Sanggeun Lee, Ramesh Harjani and Taehyoun Oh, IEEE Transactions on Circuits and Systems-II, Express Briefs, 2022

[21] A Highly Integrated Radio Frequency Receiver RF CMOS Module for Core Body Temperature Thermometer

Ikhwan Kim, Wonil Jang, Hyeon-Sik Hwang, Byeong-Jae Seo, Dong-Min Lee, Ji-Ho Han, Jae-Woo Shin, Young-Ro Yoon, Taehyoun Oh, Hyung-Chul Park, Eun-Seong Kim, Yun-Seong Eo and Nam-Young Kim, IEEE Access, 2023

[22] A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process

Kyoung-Ub Cho, Joonho Gil, Chulhyun Park, Kyu-Jin Cho, Jae-Woo Shin, Eun-Seong Kim, Yun-Seong Eo, Ramesh Harjani, Nam-Young Kim, and Taehyoun Oh, IEEE Access, 2024

[23] A 5.3 to 6.2-GHz Fractional-N Frequency Synthesizer with Variable Gain Automatic Frequency Calibration Using Cycle Slips in 65 nm CMOS 

Jinhyuk Ahn, Sangwon Kim, Kihoon Kwon, Minseo Park, Joonho Gil, Hyungkyu Choi, Nam-Young Kim, Eun-Seong Kim, Youngho Jung and Taehyoun Oh, MDPI Electronics, 2025

[24]  A 8.9 to 10-GHz −97.86-dBc Reference Spur Pulser-Free Continuous Charge Pump Sub-Sampling PLL With Fine-Tunable Dead-Zone Generator in 65-nm CMOS Process

Sangwon Kim, Kihoon Kwon, Minseo Park, Jinhyuk Ahn, Junseo Kim, Joonho Gil, Chulhyun Park, Yunseong Eo, Ramesh Harjani, Taehyoun Oh, IEEE Access, 2025

[25]  A DTC-Based Snapshot ADPLL With Feedforward Fractional Spur Cancellation and Asynchronous Duty-Modulation Dithering DCO Achieving–71.6 dBc Fractional Spur in 65-nm CMOS Process

Kihoon Kwon, Sangwon Kim, Minseo Park, Jinhyuk Ahn, Gahyeon Lee, Joonho Gil, Chulhyun Park, Yunseong Eo, Hyungkyu Choi, Chulho Kang, Eun-Seong Kim, Nam-Young Kim, Ramesh Harjani, Taehyoun Oh, IEEE Access, 2026