To implement a logical circuit using FPGA hardware via VHDL programming language in a graphical environment.
At least one Windows laptop per group is required for this session along with a USB cable that can connect your device (USB A or C to USB Micro)
Design the circuit from the FSM: Design lab in Logisim, and simulate its behavior, then record the results in a table.
Download and install the following software packages:
Open a command prompt: press windows key, and then type cmd, select the Command Prompt option that is highlighted.
Run the following commands one at a time careful of spelling. Run any recommended commands if asked along the way:
You can follow along here if you prefer (only steps 1 and 2 are necessary)
pip install apio==0.4.0b5 tinyprog
Upgrade your pip installation if requested
apio install system scons icestorm iverilog
ignore errors
apio drivers --serial-enable
ignore errors
While the integrated circuits we have seen in the lab up to this point are still found in everyday devices, they are becoming less and less common as newer technologies become cheaper and more accessible. The modern day implementation of logical circuitry is done via CPLDs (Complex Programmable Logic Devices) or FPGAs (Field Programmable Gate Arrays). These devices are essentially identical in effect, they allow the engineering or designer to program in the behavior of a desired logic circuit. The chips contain an enormous number of "blank" logic gates ready to be set up in any configuration. The versatility of these chips allows you to implement any behavior of any logical system. There are examples of users programming the entire behavior of the Apple II or MAME arcade games gate by gate into the single chips which then function exactly as the originals would. The only limiting factor is the number of gates that the chips have internally available for programming. There are cheap devices with thousands of gates, all the way up to tens of millions of gates.
The chips are programmed in a language family known as HDL (Hardware Description Language) which is a low level language that instructs the behavior of the FPGA. In this lab session, to avoid having to learn a new very complex language, we will use a GUI design suite that allows for simple designs to be created quickly while sacrificing the complex advanced abilities of the HDL. This software looks much like Logisim and will automatically generate the code that you would otherwise write for your design.
While the TinyFPGA devices look very much like Arduino or other MCU boards, the function of the FPGA devices is very different. These boards also have conveniently built the programmer and the USB interface right onto the board so they are very easy to develop with. The actual FPGA chip itself is the small square in the centre of the board. The tiny FPGA chip can be programmed to have the same functionality of hundreds or thousands of the 74xx series chips used up to this point in the lab. The TinyFPGA board uses part# ICE40LP8K from Lattice Semiconductor FPGA chips that have 7680 individual logic gates available for arrangement into whatever configuration suits the designer needs.
Start the iCEStudio software and connect to your TinyFPGA board.
Create your circuit in iceStudio, see image below or instructions to follow for described steps.
Go to Select > Board > TinyFPGA BX
Go to Edit > Preferences > Board Rules. You should get a "Board Rules Disabled" message popup.
On the right hand menu at the top, select Basic > Input
Name the input "x" and press OK, then place the part, in the drop down menu on the part, select PIN_1.
Create another input named "CLK" and and in it's drop down menu, select PIN_2.
Create a third named FCLK and in it's drop down menu select CLK.
We will use some advanced features of the FPGA to eliminate double clicks or miss clicks that you encountered using the push buttons and switches in previous labs.
Under Logic > Sequential choose Debouncer and connect the FCLK to the CLK input on the blue debouncer box.
Connect your CLK to the other input on the left hand side.
Under Logic > Sequential choose Flip-Flop D and place two on the display to the right of your two input.
Under Logic > Gate place two AND gates and one XOR gate (as used in the last lab).
Add in addition, one NOT gate since we do not have access to the Q' on the flip-flops as we did on the chips.
Click on the thin wires that come from each input and drag to attach to the appropriate output. The software will autoroute the wire for you.
you have to click at the beginning of the thin wire each time, this software doesn't not allow you to draw from mid wire.
Be sure that you have created the circuit from LAB #7
Go to Basic > Output and create one named Y1 and select PIN_3 in the drop down menu.
Create one more for Y2 and select PIN_4 from the drop down menu.
Attach each output to the D flip-flop output.
Go to Tools > Verify and you should get a green success message.
Go to Tools > Build and you should get a green success message.
Connect your TinyFPGA via USB to your laptop and wait for it to be detected.
Go to Tools > Upload and you should get a green success message.
Occasionally, if you get a BX board not detected message, it helps to press the tiny reset button on the right hand side of the board just before clicking upload.
Once you have succeeded you can unplug the USB and return it for another group to use.
If you cannot connect to your board see the instructor for help uploading.
Plug your FPGA into the Digital Lab board as you would a chip with the ins on either side of the center break (already done for you).
Do not power on your Digital Lab until your setup has been checked over.
Connect 5V to to the pin to the right of the USB port labelled Vin and connect ground to the pin opposite it labelled "G" on the left of the USB port.
Attach a Logic Switch to the pin labelled "1".
Attach a Logic Switch to the pin labelled "2".
Attach one LED to each of the pins labelled "3" & "4"
Have the instructor check your setup.
Simulate the different inputs and record them next to your Logisim results.
Set X low and verify that no changes occur.
moving the data switch attached to CLK high and low will simulate a clock.
Set X high and simulate the desired pattern.
Note that you may occasionally "double click" . The FPGA are very fast devices and can pick up flutter in the switches just millionths of a second long. Our input clock helps prevent this but it is a possibility.
with some intermediate state, set X low and verify that the state machine returns to 0 on the next clock cycle.
Did the FPGA simulation behave as expected based on the Logisim simulation?
List 5 pros and 5 cons of using an FPGA over traditional logic gates in a project.
Reference points from the design, development, and construction portions of a project.