You may wish to try out the Logisim simulation to help you understand the operation of these units.

Procedure

Note the resistor connecting Logic Switch 1 to the Debounced PB #2. Leave this in place and ensure Logic Switch 1 is in the high position.

Chip Pin # and Function Connect to

• • (74LS74) Pin 14 Vcc &

  • (74LS75) Pin 5 Vcc -> +5V

• • (74LS74) Pin 7 GND &

  • (74LS75) Pin 12 GND -> GND

• • (74LS74) Pin 2 D &

  • (74LS75) Pin 2 D -> Data Switch 8

• • (74LS74) Pin 3 CLK   &

  • (74LS75) Pin 13 Enable ->  Top Holes in Debounced PB#2.

• • (74LS74) Pin 1 CLEAR -> Logic Switch 4

• • (74LS74) Pin 4 SET -> Logic Switch 5

• • (74LS74) Pin 5 Q -> Logic Indicator LED 1

• • (74LS75) Pin 16 Q -> Logic Indicator LED 2

Test the SET and CLEAR inputs of the 74LS74 and note they are asynchronous and override the clocks determination of update timing.

1. • The set and clear on this chip  are ACTIVE LOW. This means that they take effect when set logic low or to "0".

   • When SET is 0, the flip-flop is forced to the "1" state. This will override any other behavior.

   • When CLEAR is 0, the flip-flop is forced to the "0" state. This will override any other behavior.

   • These two inputs must be in the "1" or "Logic High" state to observe the normal behavior of the flip-flop.

   • The latch does not have set/clear functionality.

Go through the timing diagram you created in Section 2 of the Prelab filling in the observed outputs. Be sure to begin with each chip in the "0" state.

1. • You should follow the ordering of the signal transition by either pressing or releasing the pulse switch for the clock, or flipping the switch for D.

   • Focus on whether a signal transitions high to low or visa-versa and in what order you do not have to run the two inputs simultaneously

   • The speed at which you do the transitions does not effect the result, so take your time.

As an example, at the beginning of the timing diagram, signal D is low (so the D-Switch, which we assigned to Logic Switch #8, should be low) and the CLK signal is low (so the pushbutton is not pressed). 

Then, D transitions high during the first clock pulse. So to simulate this, we would push the PB#2 to bring the clock signal high, and before releasing PB#2 slide the LS#8 high to bring D high. Then we can release PB#2 to return CLK to the low state.

Once we have observed the result on the LEDs, we can slide LS#8 to the low position as shown in the timing diagram to simulate signal D going Low again. 

Continue with this methodology and observation to complete the timing diagram for both signals. Draw both timing signals (7474 & 7475) as you go.

Conclusions

1. Explain how CLK, D, and Q-output are related for the latch and the flip-flop.

   • Essentially, which moments/periods are each of the 7474 (D+ FF) and 7475 (D Latch) "responsive" for and what influences the response?

2. Comment on how the asynchronous SET and CLEAR inputs work with the flip-flop.