Device input file

This is an ASCII input file for the program PHIsim_input. It describes the optical circuit that is to be simulated and the in and output points for time dependent data going in or coming out of the simulation. The file has three sections for to describe the circuit:

1. a list of components in the circuit - each line in the file describes one component. The circuit will be built using the components that are entered in the list. SO each waveguide, amplifier, modulator etc.

2. a list of connections between components - each line in the file describes one connection in the circuit.

3. a list of sources for DC current or DC voltage/phase values applied to amplifier/absorber/phase modulators.

The components

The files starts with a series of lines where each line describes one component in the circuit. Each line is structured:

name type_id [other parameters] # plus any text e.g with comments

The list ends with -1 -1 #

The line starts with a name for the component. One can choose any name with characters and numbers. Space, tab and new-line are separators so these cannot be part of a name. The name can be 512 characters long (not advisable though).

The name is followed by the type_id. This is a number that identifies the type of component.

The type_id is followed by the other parameters for the component this information depends on the component type. All possible component types, their id-numbers and the parameters required are listed on the page Circuit components. The line ends with a separator character and some other text. As standard I am using a # sign followed by a comment to make the file readable.

Currently the limit is 100 components, but this can be increased. (needs recompiling).

Two components in the list need to be special IO components, these must always be in the circuit (but you can change the name):

IO_left__ 8 # this always needs to be in the device input file

IO_right_ 9 # this always need to be in the device input file

The connections

The list of connections consists of lines where each line describes one connection. Each line has the following structure:

name_comp_left port_ID_comp_left name_comp_right port_ID_comp_right # plus any text e.g with comments

The list ends with a line xxx -1 xxx -1 # .

The line makes that there is an optical connection between a component on the left hand side (name_comp_left) and a components on the right hand side (name_comp_right). Now a component can have multiple connections on the left and the right hand side. Each possibility for a connection on a component is named a port. For instance a splitter can have one port on the left and two ports on the right. That is why there is always a port_ID after the name. The port_ID is the character R or L (a port on the right hand side of the component, or on the left) plus a number starting from 0. E.g. R0, or L1 are port_IDs.

The sources

Several types of component (amplifiers and phase modulators) need current of a phase or voltage setting which is provided by sources. Each line in this part of the input file describes the information on a source. The information on which components it is connected is in the components list. Many components of the same type may be connected to the same source. The current is then spread evenly over all segments in all components thus keeping e.g. the current density constant.

For each source in the circuit there is one line:

source_number value # plus any text e.g with comments

The source is identified by its source_number. Sources have to be numbered 0, 1, 2, 3, ... There can be as many sources as components. The source numbers are first used in the components list where the number is connected to one or more components. See the page on the Circuit components. The meaning of the value depends on the type of component it is connected to. Again please see the circuit component descriptions. If the value > 9999.0 then the source value is time dependent. The value for the source is then read from the signals input file. For each time dependent source an extra column is expected in that file with the value of the source at each time step in the simulation.

Extra lines can be inserted where the first character on the line is a '#'. These lines are ignored and comments may be placed after the #. In this way the readability of the file can be improved.

It is easy to make a mistake in this input file, particularly in the list of connections. Therefore the PHIsim_input program generates a file for a diagram, depicting the components, connections and sources input.

Warning

A word of warning. There actually aren't many warnings generated by the software. Not much attention has been paid to incorrect input. So syntax errors in the files may lead to unexpected results. If this happens and it annoys you, just remember this software is for free and write a nice mail with your suggestions for improvements.

- The device input file must be correct

- There must be no open connections

- All components must thus be in use (connected)

If this is not the case, the program simply crashes.

An example file in detail

This input file below describes a ringlaser with a 2x2 coupler as an output coupler and a small reflection in the waveguide on the coupler at the left. There is single source supplying current (0.3 Amp).

IO_left__ 8 # this always needs to be there

IO_right_ 9 # idem

pas_wg_L1 1 10 # passive waveguide

reflect_L 5 0.01 0.0 # reflection type5

pas_wg_L2 1 10 # passive waveguide

coupler22 103 # 2 x 2 coupler

pas_wg_R1 1 10 # passive waveguide

soa_ring_ 2 100 0 # amplifier

-1 -1 # end of component list - start of connections list

IO_left__ R0 pas_wg_L1 L0 #

pas_wg_L1 R0 reflect_L L0 #

reflect_L R0 pas_wg_L2 L0 #

pas_wg_L2 R0 coupler22 L0 #

coupler22 R0 pas_wg_R1 L0 #

pas_wg_R1 R0 IO_right_ L0 #

coupler22 R1 soa_ring_ L0 #

soa_ring_ R0 coupler22 L1 #

xxx -1 xxx -1 # end of connections list - start of current source list

0 0.3 # current source 0

-1 -1 # end of current source list

More example files