A project in SVEditor terms is defined as a collection of files that work together. A project could be:
Generally it is something that you would simulate.
This topic has been covered extensively in the tutorials section. Please refer to this for more details.
You can open the project properties page from the Project Explorer window. Inside this page you will see a number of tabs.
The resource page has 2 tabs:
Path Variables
Path variables are fairly commonly used in design flows. These are typically used to reference paths outside of a given user sandbox. Variables can be created using the "New" button.
The System Verilog Project Properties section of the project properties has 4 tabs:
This section of the project contains a list of all the argument file(s) that your project will use. A typical argument file contains
Argument files can be added using the "Add" button, or directly from the Project Explorer window by right clicking on the argument file and selecting Add argument file to project
This section can be used to add defines to the index (compile) section. Typically these switches are used during compilation to include or exclude certain pieces of code that are `ifdef'ed out, or to parameterize code on the command line. The command line will often include +define+SOMEDEFINE.
These definitions can be added here.