Tutorial: Project Management

Project Management

In Eclipse terms, a project is a group of related files. As a Verilog designer / verification engineer, this can be:

• A chip
• A piece of synthesizable IP
• A piece of verification IP
• A piece of IP that contains all deliverables (verification, RTL, constraints etc.)

As designers/verification engineers we continually switch between "Projects" so project management is an important part of what we do. Projects can either be

• Closed and opened (still visible within the workspace)
• Deleted & Imported (Removed from the workspace)

This tutorial assumes you have a project loaded. In the specific examples below I am using the tutorial you would have loaded in the "Getting Started" section, but any project(s) will do. The Getting Started tutorial used the code in this zip file.

Multiple Projects & Environment Variables

Often times a user will want to have 2 designs loaded simultaneously. Assume 2 areas that are checked out of the same repository, on different tags. The file sets are almost identical, but there are subtle differences that you want to take a look at. Environment variables are often used to differentiate between areas. SVEditor supports the scenario where you have 2 projects, with near identical argument files where the only difference is a series of environment variables to differentiate between them. Below is an excerpt from a typical argument file:

// Load a piece of RTL

${PATH_TO_IP}/rtl/top.sv

When SVEditor comes across ${PATH_TO_IP} it will first look for the variable in the project settings, then in the environment of the terminal that SVEditor was launched from. This means that you can set ${PATH_TO_IP} to have different variables based on the project it is in.

The following example loads a second design (Project).

1. File>New>SVE Project
2. Next
3. Set the "Project Name" to "chip2"
4. Uncheck "Use Default Location" and browse to where you unzipped the project. In this will be something like "C:\<...>\chip2"
5. Add the files.f in "chip2/sim/files.f"
6. Hit Finish
7. At this point Chip1 and Chip2 will be loaded

1. Open chip2's files.f
   1. Ctrl+Shift+R>files.f
   2. Note that this also refers to the environment variable "CHIP" in the paths to the files
   3. This has not been defined for chip2 which results in error markers being shown in the argument file
2. Add the variable CHIP to the project chip
   1. Right Click on chip2>Properties>Resource>Linked Resources.
   2. Set the variable CHIP to reference the variable ${project_loc}
3. Now have Eclipse compile Chip 2
   1. Project>Clean