There are many ways to contribute to SVEditor -- independent of whether you know Java.
SVEditor's SystemVerilog parser is at the heart of the tool, and is continually being improved. Ensuring that the parser correctly handles SystemVerilog language constructs is a critical QA task. Providing SystemVerilog code that can be included in SVEditor's test suite is one important way to contribute to the project.
SystemVerilog (or Verilog) code needs to be distributed under an Open Source license. For example, SVEditor currently uses some projects from the OpenCores.org site.
Content-assist templates provide content assist for implementing a language feature. For example, the Eclipse Java IDE provides a content-assist template for the 'for' construct that prompts the user to fill in the required elements of the 'for' statement.
Developing a content-assist template does not require any Java code -- just knowledge of the SystemVerilog feature and a few textual conventions.
SVEditor provides several built-in file-creation templates to create starting points for common styles of SystemVerilog and UVM classes. Create a new template or two to contribute to SVEditor, and the entire community benefits!
Everyone develops SystemVerilog in slightly different ways. When you encounter unexpected behavior in SVEditor, filing a bug ensures that SVEditor will support your method of developing SystemVerilog.
Many times, specifying all the details of a new feature is as much work as writing the code to implement that feature. File new feature requests using the 'Feature Requests' tracker.
Certain areas of functionality require many tests that (from a Java perspective) are all nearly identical. The distinguishing characteristic is the SystemVerilog code processed by the test.
Two areas that fit this pattern are:
The SystemVerilog language is extremely large. Enhancing the portions of the language handled by the parser is a key area of work. If you would like to contribute please review the pages below.