Metal-Gate/High-K CMOS Technology (金屬閘極/高介電質CMOS製程技術) 

A major challenge for metal-gate/high-k CMOS is to trade off equivalent oxide thickness (EOT) and flat-band voltage (Vfb) roll-off at a CMOS-compatible gate first process, since the large Vfb roll-off at smaller EOT is undesirable, which can result in an unwanted high Vt. Although an ultra-thin SiO2 layer can be used as interface layer between high-k dielectric and Si to reach a 1-nm EOT in the 45 nm node technology, this may not work as the gate-stack technology is highly scaled down to sub-0.6-nm EOT for 16 nm technology node.