CCT203 Computer Architecture & Data Communication

Assessment Rubric

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Assignment: 25%

Test: 25%

Exam: 50%

Important MUST-KNOW topic

- Fetch Execute cycle

- Addressings

- Replacement Policy

- Subroutine

- RPN

Chapter 1: CPU

Question

Using MUL 60, 65, 77 show the fetch and execute cycle?

Sample Answer

Fetch Cycle:

PC -> MAR -> Address Bus

Read control line asserted

MUL[60][65][77] -> databus -> MBR -> IR

PC=PC+1 

Execute Cycle:

IR – Decoding 

60 -> MAR -> Address bus 

Read control line asserted

[data]60 -> databus -> MBR -> ACC

65 -> MAR -> Address bus 

Read control line asserted

[data]65 -> databus -> MBR -> ACC

77 -> MAR -> Address bus

Write control line asserted 

[result]77 <- databus -> MBR <- ACC

Common interrupts that the CPU can receive

-Program: Generated by some condition that occurs as a result of an instruction execution, such as arithmetic overflow, division by zero, attempt to execute an illegal machine instruction, and reference outside a user's allowed memory space.

-Timer: Generated by a timer within the processor. This allows the operating system to perform certain functions on a regular basis.

-I/O: Generated by an I/O controller, to signal normal completion of an operation or to signal a variety of error conditions.

-Hardware failure: Generated by a failure such as power failure or memory parity error.

Pipelining is possible by having separate hardware units.

Chapter 2 Computer Instruction

Question

A computer system has a 40-bit wide instruction word with 4 bits for opcode and 36 bits for the operands. How many bits would be allocated to each of the operand and what would be the total addessable range of the instruction formats given as a 2 address format.

Sample Answer

36 bit for operand

36/2 = 18 bit for each operand

218 = 262,144 (256Kb)

Chapter 4: Stacks & Subroutines

Question:

Find the Polish Notation of the expresion (U + V) / [W * (X + Y) - Z]

Sample Answer

UV+WXY+*Z-/

Question:

Reverse Polish notation combined with a stack provides an efficient way to evaluate arithmetic expressions. Explain with diagram the stack operation on arithmetic expression given in the RPN notation.

10 2 * 8 4 / +

Sample Answer

Chapter 6: Memory Organization

Question

A stream of address 4, 4, 2, 4, 5, 5, 2, 3, 6 is entered into a cache memory which can only contain 3 page address at a time.

Using LRU, show the status of the cache memory indicating hits if any.

Sample Answer

Question

A stream of address 6, 7, 6, 5, 9, 6, 8, 9, 7, 6 is to be entered serially into the cache memory which can only contain 3 page addresses at a time. Show this using the LRU replacement policy.

Sample Answer

Chapter 8 TCP/IP & WAP Protocols

Best Regards,